Automated Analog Circuit Synthesis using a Linear Representation

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eaches the last component to place in the circuit, we arbitrarily chose to havethe last node (value in CN) connected to the output terminal by a wire. Bydoing so, we eliminate unconnected branches.We had two goals in designing the above encoding scheme. First, we wantedto see if a very simple set of primitives encoded in a linear fashion could indeedbe used to successfully evolve circuits. Second, we wanted to minimize computertime during the genetic algorithm run. By keeping the decoding process minimal,the total time for tness evaluations is thus reduced. Along the same lines, wewanted to keep circuit \repair" operations (e.g., removal of unconnected nodes)to a minimum since these also slow the system down.The most signicant restriction of our technique is that it cannot supportall possible circuit topologies: circuit branches o of the main \constructingthread" cannot, in general, contain more than one node (there are some exceptionsto this). The constructing thread is the sequence of components that arecreated by the x-move-to-new opcode. The constructing thread itself can be ofvarying lengths and can contain both series and parallel congurations. In spiteof these limitations, our system allows creation of circuits with a large varietyof topologies, especially topologies seen in hand-designed circuits (e.g., ladderconstructs). We have lessened the topology restrictions somewhat by allowing\move-to" opcodes and will report on these eorts in the future.3 Genetic AlgorithmThe genetic algorithm operates on a population of dynamically-sized bytecodearrays. In practice we imposed a maximum size of about 400 bytes (100 circuitcomponents) in order to accommodate population sizes of up to 18,000 individualsin our GA runs. The crossover and mutation (per locus) rates were setat 0.8 and 0.2 respectively. An overview of the evaluation process is depictedin Fig. 2. As in the GP system mentioned above, we used the Berkeley SPICEcircuit simulation program to simulate our circuits. The array ofbytecodes wasinterpreted in the manner previously described, and resulted in a SPICE netlistrepresentation. The netlist is processed by SPICE and the output is then usedto compute tness for the individual. Fitness was calculated as the absolutevalue of the dierence of the individual's output and the target output. Theseerror values were summed across evaluation points, with error being the distancebetween the target and the value the individual produced.The parallel genetic algorithm implemented uses master/slave style parallelism[2] over a network of UNIX-based computers. A controlling host computerperforms GA functions and distributes a population of bytecoded-individuals tospecied number of worker nodes using socket connections. The worker nodesdecode the individuals into SPICE netlists which are then fed into SPICE viaFIFO pipes to minimize disk activity. Fitness is calculated using SPICE's output,and then sent back to the host. Hundreds of individuals (and tness scores)are packaged into a single message so that external network congestion delays areminimized. The SPICE program itself required little modication since it runs
ytecodesnetlistdecodeSPICEcircuitsimulationfitnesscalculationFig. 2. Overview of circuit evaluation process starting with bytecoded representationand ending with tness score.as a separate process. Written in the C programming language, the system currentlyruns on Sun workstations and is portable to other UNIX systems (e.g., wehave ported the software to PCs running UNIX). This allows the system to runon UNIX-based clusters comprised of computers from dierent manufacturers.4 Experimental ResultsWe attempted to evolve twoanalog lter circuits. The choice of using passiveanalog lters was inspired by the previous studies and is a good choice for testingthe eectiveness of our system for three reasons. First, all components havetwo-terminals, the minimum number possible. If the proposed system could notevolve useful circuits using two-terminaled devices, then attempting to evolvecircuits using more complex components (e.g., transistors) would likely proveineective. Second, there are no energy sources required within the circuit whichfurther reduces the complexity. Lastly, lter design is a well-understood disciplinewithin circuit design. Its \design space" has been greatly explored [7] whichallows us to compare our evolved designs to well-known designs.The problems we present below are both low-pass lters. A low-pass lter isa circuit the allows low frequencies to pass through it, but stops high frequenciesfrom doing so. In other words, it \lters out" frequencies above a speciedfrequency. The unshaded area in Fig. 3 depicts the region of operation for lowpasslters. Below the frequency f p the input signal is passed to the output,potentially reduced (attenuated) by K p decibels (dB). This region is known asthe passband. Above the frequency f s , the input signal is markedly decreasedby K s decibels. As labeled, this region is called the stopband. Between the passbandand stopband the frequency response curve transitions from low tohighattenuation. The parameter located in this region, f c , is known as the cutofrequency.
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Automated Analog Circuit Synthesis using a Linear Representation

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