Unit I

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Reading “High” at Input PinRead latch1. write a 1 to the pin MOVP1,#0FFHTB2VccLoad(L1)2. MOV A,P1externalpin=HighInternal CPUbusDP1.XQ11P1.X pinWrite to latchClkQ0M1TB1Read pin3. Read pin=1 Readlatch=0 Write to latch=1M.Balakarthikeyan -
Reading “Low” at Input PinRead latch1. write a 1 to the pinMOV P1,#0FFHTB2VccLoad(L1)2. MOV A,P1external pin=LowInternal CPUbusDP1.XQ10P1.X pinWrite to latchClkQ0M1Read pin3. Read pin=1 Readlatch=0 Write to latch=1TB18051 ICM.Balakarthikeyan -
Page 1 and 2: The 8051MicrocontrollerM.Balakarthi
Page 3 and 4: Block DiagramExternal InterruptsInt
Page 5 and 6: Three criteria in Choosing aMicroco
Page 7: Comparison of the 8051 Family Membe
Page 10 and 11: 8051Foot Print123456789101112131415
Page 12 and 13: Port 3 Alternate FunctionsM.Balakar
Page 14 and 15: Hardware Structure of I/O PinRead l
Page 16 and 17: Writing “1” to Output Pin P1.XR
Page 20 and 21: Port 0 with PullUp ResistorsVcc10
Page 22 and 23: Pins of 8051 Vcc ( pin 40 ):Vcc pro
Page 24 and 25: XTAL Connection to an External Cloc
Page 26 and 27: Pins of 8051 RST ( pin 9 ): reset i
Page 28 and 29: RESET Value of Some 8051 Registers:
Page 30 and 31: Pins of 8051 ALE ( pin 30 ): addres
Page 32 and 33: Address Multiplexingfor External Me
Page 34 and 35: Accessing ExternalData MemoryFigure
Page 36 and 37: External code memoryWRRDPSENALEP0.0
Page 38 and 39: Overlapping External Codeand Data S
Page 40 and 41: Overlapping External Codeand Data S
Page 42 and 43: On-Chip MemoryInternal RAMM.Balakar
Page 44 and 45: Bit Addressable Memory2F2E2D2C2B2A2
Page 46 and 47: Bit Addressable RAMFigure 2-6Summar
Page 48 and 49: M.Balakarthikeyan -
Page 50 and 51: M.Balakarthikeyan -
Page 52 and 53: RegistersM.Balakarthikeyan -
Page 54 and 55: The 8051Assembly LanguageM.Balakart
Page 56 and 57: Data Transfer Instructions MOV dest
Page 58 and 59: Addressing ModesImmediate Mode - co
Page 60 and 61: Addressing ModesDirect Mode - speci
Page 62 and 63: Addressing ModesRegister Indirect -
Page 64 and 65: Addressing ModesRegister Indexed Mo
Page 66 and 67: Acc Register A register can be acce
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SFRs AddressAll SFRs such as(ACC, B
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8051 Instruction Format Register ad
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8051 Instruction Format relative ad
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Stackspushpopstack pointerstackGo d
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Stack (push,pop) ThereforePush aPus
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Bit-Oriented Data Transfer transfer
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Data Processing InstructionsArithme
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Arithmetic InstructionsMnemonicADD
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Instructions that Affect PSW bitsM.
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Signed Addition and Overflow2’s c
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The 16bit ADD example; Computes Z
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Increment and DecrementINC AINC byt
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MultiplyWhen multiplying two 8bit
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Decimal AdjustDA a; decimal adjust
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Bitwise LogicANL ANDORL ORXRL XO
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Uses of Logic Instructions Force in
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CLR ( Set all bits to 0)CLR ACLR by
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Rotate through CarryRRC aCmov a, #0
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SwapSWAP amov a, #72h ; a 27hswap
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Program Flow Control Unconditional
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Infinite LoopsStart: mov C, p3.7mov
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Jump tableMov dptr,#jump_tableMov a
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Conditional jumpsMnemonicDescriptio
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More Conditional JumpsMnemonicCJNE
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Iterative Loops(examples)mov a,#50h
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Return Return is also similar to a
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Initializing Stack Pointer SP is in
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Subroutine - another example; Progr
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example of delaymov a,#0aahBack1:mo
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Example; Move string from code memo
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Example; duty cycle 50%back: cpl p1
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M.Balakarthikeyan -8051 timer
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Interrupt Sources Original 8051 has
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Interrupt Priorities What if two in
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Interrupt VectorsEach interrupt has
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Example Interrupt Service Routine;E
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Unit I

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