Unit I

The 8051MicrocontrollerM.Balakarthikeyan -

8051 Basic Component 4K bytes internal ROM 128 bytes internal RAM Four 8­bit I/O ports (P0 ­ P3). Two 16­bit timers/counters One serial interfaceCPURAMI/OPort TimerROMSerialCOMPortA single chipMicrocontrollerM.Balakarthikeyan -

Block DiagramExternal InterruptsInterruptControl4kROM128 bytesRAMTimer 1Timer 2CPUOSCBusControl4 I/O PortsSerialP0 P2 P1 P3Addr/DataTXD RXDM.Balakarthikeyan -

Other 8051 featurs only 1 On chip oscillator (external crystal) 6 interrupt sources (2 external , 3 internal, Reset) 64K external code (program) memory(only read)PSEN 64K external data memory(can be read and write) byRD,WR Code memory is selectable by EA (internal or external) We may have External memory as data and codeM.Balakarthikeyan -

Three criteria in Choosing aMicrocontroller meeting the computing needs of the task efficiently andcost effectively speed, the amount of ROM and RAM, the number of I/O ports andtimers, size, packaging, power consumption easy to upgrade cost per unit availability of software development tools assemblers, debuggers, C compilers, emulator, simulator,technical support wide availability and reliable sources of themicrocontrollersM.Balakarthikeyan -

Comparison of the 8051 Family Members ROM type 8031 no ROM 80xx mask ROM 87xx EPROM 89xx Flash EEPROM 89xx 8951 8952 8953 8955 898252 891051 892051 Example (AT89C51,AT89LV51,AT89S51) AT= ATMEL(Manufacture) C = CMOS technology LV= Low Power(3.0v)M.Balakarthikeyan -

Comparison of the 8051 Family Members89XX ROM RAM Timer IntSourceIO pinOther8951 4k 128 2 6 32 -8952 8k 256 3 8 32 -8953 12k 256 3 9 32 WD8955 20k 256 3 8 32 WD898252 8k 256 3 9 32 ISP891051 1k 64 1 3 16 AC892051 2k 128 2 6 16 ACWD: Watch Dog TimerAC: Analog ComparatorISP: In System ProgramableM.Balakarthikeyan -

8051SchematicPin outM.Balakarthikeyan -

8051Foot Print12345678910111213141516171819204039383736353433323130292827262524232221P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST(RXD)P3.0(TXD)P3.1(T0)P3.4(T1)P3.5XTAL2XTAL1GND(INT0)P3.2(INT1)P3.3(RD)P3.7(WR)P3.6VccP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)8051(8031)(8751)(8951)M.Balakarthikeyan -

IMPORTANT PINS (IO Ports) One of the most useful features of the 8051 is that it contains four I/O ports (P0 -P3) Port 0 ( pins 32­39 ): P0 ( P0.0 ~ P0.7 ) 8­bit R/W ­ General Purpose I/O Or acts as a multiplexed low byte address and data bus for external memory design Port 1 ( pins 1­8 ) : P1 ( P1.0 ~ P1.7 ) Only 8­bit R/W ­ General Purpose I/O Port 2 ( pins 21­28 ): P2 ( P2.0 ~ P2.7 ) 8­bit R/W ­ General Purpose I/O Or high byte of the address bus for external memory design Port 3 ( pins 10­17 ): P3 ( P3.0 ~ P3.7 ) General Purpose I/O if not using any of the internal peripherals (timers) or external interrupts. Each port can be used as input or output (bi-direction)M.Balakarthikeyan -

Port 3 Alternate FunctionsM.Balakarthikeyan -

8051 Port 3 Bit Latches and I/O BuffersM.Balakarthikeyan -

Hardware Structure of I/O PinRead latchTB2VccInternalCPU busWrite tolatchDP1.XClkQQLoad(L1)M1P1.XpinRead pinTB1M.Balakarthikeyan -

Hardware Structure of I/O Pin Each pin of I/O ports Internally connected to CPU bus A D latch store the value of this pin Write to latch = 1 : write data into the D latch 2 Tri­state buffer : TB1: controlled by “Read pin”Read pin = 1 : really read the data present at the pin TB2: controlled by “Read latch”Read latch = 1 : read value from internal latch A transistor M1 gate Gate=0: open Gate=1: closeM.Balakarthikeyan -

Writing “1” to Output Pin P1.XRead latch1. write a 1 to theLoad(L1)Internal pin D Q1P1.XCPU busP1.Xpin0 output 1M1Write tolatchClkQTB2Vcc2. output pinis VccRead pinTB1M.Balakarthikeyan -

Writing “0” to Output Pin P1.XRead latch1. write a 0 to theLoad(L1)Internal pin D Q0P1.XCPU busP1.Xpin1 output 0M1Write tolatchClkQTB2Vcc2. output pinis groundRead pinTB1M.Balakarthikeyan -

Reading “High” at Input PinRead latch1. write a 1 to the pin MOVP1,#0FFHTB2VccLoad(L1)2. MOV A,P1externalpin=HighInternal CPUbusDP1.XQ11P1.X pinWrite to latchClkQ0M1TB1Read pin3. Read pin=1 Readlatch=0 Write to latch=1M.Balakarthikeyan -

Reading “Low” at Input PinRead latch1. write a 1 to the pinMOV P1,#0FFHTB2VccLoad(L1)2. MOV A,P1external pin=LowInternal CPUbusDP1.XQ10P1.X pinWrite to latchClkQ0M1Read pin3. Read pin=1 Readlatch=0 Write to latch=1TB18051 ICM.Balakarthikeyan -

Port 0 with Pull­Up ResistorsVcc10 KDS500087518951P0.0P0.1P0.2P0.3P0.4P0.5P0.6P0.7Port 0M.Balakarthikeyan -

IMPORTANT PINSPSEN (out): Program Store Enable, the readsignal for external program memory (active low). ALE (out): Address Latch Enable, to latch addressoutputs at Port0 and Port2 EA (in): External Access Enable, active low toaccess external program memory locations 0 to 4K RXD,TXD: UART pins for serial I/O on Port 3 XTAL1 & XTAL2: Crystal inputs for internaloscillator.M.Balakarthikeyan -

Pins of 8051 Vcc ( pin 40 ):Vcc provides supply voltage to the chip.The voltage source is +5V. GND ( pin 20 ): ground XTAL1 and XTAL2 ( pins 19,18 ):These 2 pins provide external clock.Way 1 : using a quartz crystal oscillatorWay 2 : using a TTL oscillatorExample 4­1 shows the relationship betweenXTAL and the machine cycle.M.Balakarthikeyan -

XTAL Connection to 8051 Using a quartz crystal oscillator We can observe the frequency on the XTAL2 pin.C230pFC1XTAL230pFXTAL1GNDM.Balakarthikeyan -

XTAL Connection to an External Clock Source Using a TTL oscillator XTAL2 is unconnected.NCEXTERNALOSCILLATORSIGNALXTAL2XTAL1GNDM.Balakarthikeyan -

Machine cycleFind the machine cycle for(a) XTAL = 11.0592 MHz(b) XTAL = 16 MHz.Solution:(a) 11.0592 MHz / 12 = 921.6 kHz; machine cycle = 1 / 921.6 kHz = 1.085 µs(b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 µsM.Balakarthikeyan -

Pins of 8051 RST ( pin 9 ): reset input pin and active high ( normally low ) .The high pulse must be high at least 2machine cycles. power­on reset.Upon applying a high pulse to RST, themicrocontroller will reset and all values inregisters will be lost.Reset values of some 8051 registers power­on reset circuitM.Balakarthikeyan -

Power­On RESETVcc10 uF30 pF31EA/VPPX19X2RST8.2 KM.Balakarthikeyan -

RESET Value of Some 8051 Registers:RegisterPCACCBPSWSPDPTRReset Value000000000000000000070000M.Balakarthikeyan -RAM are all zero

Pins of 8051 /EA ( pin 31 ): external access There is no on-chip ROM in 8031 and 8032 . The /EA pin is connected to GND to indicate the code is storedexternally. /PSEN & ALE are used for external ROM. For 8051, /EA pin is connected to Vcc. “/” means active low. /PSEN ( pin 29 ): program store enable This is an output pin and is connected to the OE pin of theROM. See Chapter 14.M.Balakarthikeyan -

Pins of 8051 ALE ( pin 30 ): address latch enableIt is an output pin and is active high.8051 port 0 provides both address and data.The ALE pin is used for de-multiplexing theaddress and data by connecting to the G pin ofthe 74LS373 latch.M.Balakarthikeyan -

Address Multiplexingfor External MemoryFigure 2-7Multiplexingthe address(low-byte)and databusM.Balakarthikeyan -

Address Multiplexingfor External MemoryFigure 2-8AccessingexternalcodememoryM.Balakarthikeyan -

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Accessing ExternalData MemoryFigure 2-11Interfaceto 1KRAMM.Balakarthikeyan -

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External code memoryWRRDPSENALEP0.0P0.7GD74LS373OECSA0A7EAP2.0P2.7D0D7A8A158051ROMM.Balakarthikeyan -

External data memoryWRRDPSENALEP0.0P0.7GD74LS373WRRDCSA0A7EAP2.0P2.7D0D7A8A15M.Balakarthikeyan -8051 RAM

Overlapping External Codeand Data SpacesM.Balakarthikeyan -

Overlapping External Codeand Data SpacesWRRDPSENALEP0.0P0.7GD74LS373WRRDCSA0A7EAP2.0P2.7D0D7A8A158051RAMM.Balakarthikeyan -

Overlapping External Codeand Data SpacesAllows the RAM to be written as data memory, and read as data memory as well as code memory.This allows a program to bedownloaded from outside into the RAM as data, and executed from RAM as code.M.Balakarthikeyan -

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On-Chip MemoryInternal RAMM.Balakarthikeyan -

Registers1F1817Bank 3Bank 2Four Register BanksEach bank has R0-R7Selectable by psw.2,3100FBank 1080706050403020100R7R6R5R4R3R2R1R0Bank 0M.Balakarthikeyan -

Bit Addressable Memory2F2E2D2C2B2A292827262524232221207F 7820h – 2Fh (16 locations X 8­bits = 128 bits)Bit addressing:mov C, 1Ahormov C, 23h.2M.Balakarthikeyan -

Special Function RegistersDATA registersCONTROL registersTimersSerial portsInterrupt systemAnalog to Digital converterDigital to Analog converterEtc.Addresses 80h – FFhDirect Addressing used toaccess SPRsM.Balakarthikeyan -

Bit Addressable RAMFigure 2-6Summaryof the 8051on-chipdatamemory(RAM)M.Balakarthikeyan -

Bit Addressable RAMFigure 2-6Summaryof the 8051on-chipdatamemory(SpecialFunctionRegisters)M.Balakarthikeyan -

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Register Banks Active bank selected by PSW [RS1,RS0] bit Permits fast “context switching” in interruptservice routines (ISR).M.Balakarthikeyan -

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8051 CPU RegistersA (Accumulator)BPSW (Program Status Word)SP (Stack Pointer)PC (Program Counter)DPTR (Data Pointer)Used in assemblerinstructionsM.Balakarthikeyan -

RegistersM.Balakarthikeyan -

RegistersABR0R1DPTRDPHDPLR2R3R4R5R6R7Some 8­bitRegisters of the8051PCPCSome 8051 16­bit RegisterM.Balakarthikeyan -

The 8051Assembly LanguageM.Balakarthikeyan -

Overview Data transfer instructions Addressing modes Data processing (arithmetic and logic) Program flow instructionsM.Balakarthikeyan -

Data Transfer Instructions MOV dest, source Stack instructionsdest sourcePUSH byte ;increment stack pointer,;move byte on stackPOP byte;move from stack to byte,;decrement stack pointer Exchange instructionsXCH a, byte ;exchange accumulator and byteXCHD a, byte ;exchange low nibbles of;accumulator and byteM.Balakarthikeyan -

Addressing ModesImmediate Mode – specify data by its valuemov A, #0 ;put 0 in the accumulator;A = 00000000mov R4, #11h;put 11hex in the R4 register;R4 = 00010001mov B, #11 ;put 11 decimal in b register;B = 00001011mov DPTR,#7521h ;put 7521 hex in DPTR;DPTR = 0111010100100001M.Balakarthikeyan -

Addressing ModesImmediate Mode – continueMOV DPTR,#7521hMOV DPL,#21HMOV DPH, #75COUNT EGU 30~~mov R4, #COUNTMOV DPTR,#MYDATA~~0RG 200HMYDATA:DB “IRAN”M.Balakarthikeyan -

Addressing ModesRegister Addressing – either source or destination is one ofCPU registerMOV R0,AMOV A,R7ADD A,R4ADD A,R7MOV DPTR,#25F5HMOV R5,DPLMOV R,DPHNote that MOV R4,R7 is incorrectM.Balakarthikeyan -

Addressing ModesDirect Mode – specify data by its 8­bit addressUsually for 30h­7Fh of RAMMov a, 70hMov R0,40hMov 56h,aMov 0D0h,a; copy contents of RAM at 70h to a; copy contents of RAM at 70h to a; put contents of a at 56h to a; put contents of a into PSWM.Balakarthikeyan -

Addressing ModesDirect Mode – play with R0­R7 by direct addressMOV A,4 ≡ MOV A,R4MOV A,7 ≡ MOV A,R7MOV 7,2 ≡ MOV R7,R6MOV R2,#5MOV R2,5;Put 5 in R2;Put content of RAM at 5 in R2M.Balakarthikeyan -

Addressing ModesRegister Indirect – the address of the source or destination is specifiedin registersUses registers R0 or R1 for 8­bit address:mov psw, #0 ; use register bank 0mov r0, #0x3Cmov @r0, #3 ; memory at 3C gets #3; M[3C] 3Uses DPTR register for 16­bit addresses:mov dptr, #0x9000 ; dptr 9000hmovx a, @dptr; a M[9000]Note that 9000 is an address in external memoryM.Balakarthikeyan -

Use Register Indirect to accessupper RAM block (+8052)M.Balakarthikeyan -

Addressing ModesRegister Indexed Mode – source or destinationaddress is the sum of the base address and theaccumulator(Index) Base address can be DPTR or PCmov dptr, #4000hmov a, #5movc a, @a + dptr ;a M[4005]M.Balakarthikeyan -

Addressing ModesRegister Indexed Mode continueBase address can be DPTR or PCORG 1000h1000 mov a, #5PC1002 movc a, @a + PC ;a M[1008]1004 NopTable LookupMOVC only can read internal code memoryM.Balakarthikeyan -

Acc Register A register can be accessed by direct and register mode This 3 instruction has same function with different code0703 E500 mov a,00h0705 8500E0 mov acc,00h0708 8500E0 mov 0e0h,00h Also this 3 instruction070B E9070C 89E0070E 89E0mov a,r1mov acc,r1mov 0e0h,r1M.Balakarthikeyan -

SFRs Address B – always direct mode ­ except in MUL & DIV0703 8500F0 mov b,00h0706 8500F0 mov 0f0h,00h0709 8CF0 mov b,r4070B 8CF0mov 0f0h,r4 P0~P3 – are direct address0704 F580 mov p0,a0706 F580 mov 80h,a0708 859080 mov p0,p1 Also other SFRs (pcon, tmod, psw,….)M.Balakarthikeyan -

SFRs AddressAll SFRs such as(ACC, B, PCON, TMOD, PSW, P0~P3, …)are accessible by name and direct addressButboth of themMust be coded as direct addressM.Balakarthikeyan -

8051 Instruction Format immediate addressingOp codeImmediate dataadd a,#3dh;machine code=243d Direct addressingOp codeDirect addressmov r3,0E8h;machine code=ABE8M.Balakarthikeyan -

8051 Instruction Format Register addressingOp coden n n070D E8 mov a,r0 ;E8 = 1110 1000070E E9 mov a,r1 ;E9 = 1110 1001070F EA mov a,r2 ;EA = 1110 10100710 ED mov a,r5 ;ED = 1110 11010711 EF mov a,r7 ;Ef = 1110 11110712 2F add a,r70713 F8 mov r0,a0714 F9 mov r1,a0715 FA mov r2,a0716 FD mov r5,a0717 FD mov r5,aM.Balakarthikeyan -

8051 Instruction Format Register indirect addressingOp codeimov a, @Ri ; i = 0 or 1070D E7070D 93070E 83070F E0mov a,@r1movc a,@a+dptrmovc a,@a+pcmovx a,@dptr0710 F0 movx @dptr,a0711 F2 movx @r0,a0712 E3 movx a,@r1M.Balakarthikeyan -

8051 Instruction Format relative addressingOp code Relative addresshere: sjmp here ;machine code=80FE(FE=-2)Range = (-128 ~ 127) Absolute addressing (limited in 2k current mem block)A10-A8Op code0700 1 org 0700hA7-A007FEh0700 E106 2 ajmp next ;next=706h0702 00 3 nop0703 00 4 nop0704 00 5 nop0705 00 6 nop7 next:8 endM.Balakarthikeyan -

8051 Instruction Format Long distance addressOp code A15-A8 A7-A0Range = (0000h ~ FFFFh)0700 1 org 0700h0700 020707 2 ajmp next ;next=0707h0703 00 3 nop0704 00 4 nop0705 00 5 nop0706 00 6 nop7 next:8 endM.Balakarthikeyan -

Stackspushpopstack pointerstackGo do the stack exercise…..M.Balakarthikeyan -

Stack Stack­oriented data transfer Only one operand (direct addressing) SP is other operand – register indirect ­ implied Direct addressing mode must be used in Push and Popmov sp, #0x40; Initialize SPpush 0x55; SP SP+1, M[SP] M[55]; M[41] M[55]pop b ; b M[55]Note: can only specify RAM or SFRs (direct mode) to push or pop.Therefore, to push/pop the accumulator, must use acc, not aM.Balakarthikeyan -

Stack (push,pop) ThereforePush aPush r0Push r1;is invalid;is invalid;is invalidpush acc ;is correctPush psw ;is correctPush b;is correctPush 13hPush 0Push 1Pop 7Pop 8Push 0e0h ;accPop 0f0h ;bM.Balakarthikeyan -

Exchange Instructionstwo way data transferXCH a, 30h ; a M[30]XCH a, R0XCH a, @R0XCHD a, R0; a R0; a M[R0]; exchange “digit”a[7..4] a[3..0]R0[7..4] R0[3..0]Only 4 bits exchangedM.Balakarthikeyan -

Bit-Oriented Data Transfer transfers between individual bits. Carry flag (C) (bit 7 in the PSW) is used as a singlebitaccumulator RAM bits in addresses 20­2F are bit addressablemov C, P0.0mov C, 67hmov C, 2ch.7M.Balakarthikeyan -

SFRs that are Bit AddressableSFRs with addressesending in 0 or 8 arebit­addressable.(80, 88, 90, 98, etc)Notice that all 4parallel I/O ports arebit addressable.M.Balakarthikeyan -

Data Processing InstructionsArithmetic InstructionsLogic InstructionsM.Balakarthikeyan -

Arithmetic Instructions Add Subtract Increment Decrement Multiply Divide Decimal adjustM.Balakarthikeyan -

Arithmetic InstructionsMnemonicADD A, byteADDC A, byteSUBB A, byteINC AINC byteINC DPTRDEC ADEC byteMUL ABDIV ABDA ADescriptionadd A to byte, put result in Aadd with carrysubtract with borrowincrement Aincrement byte in memoryincrement data pointerdecrement accumulatordecrement bytemultiply accumulator by b registerdivide accumulator by b registerdecimal adjust the accumulatorM.Balakarthikeyan -

ADD Instructionsadd a, byteaddc a, byte; a a + byte; a a + byte + CThese instructions affect 3 bits in PSW:C = 1 if result of add is greater than FFAC = 1 if there is a carry out of bit 3OV = 1 if there is a carry out of bit 7, but not from bit 6, or visaversa.M.Balakarthikeyan -

Instructions that Affect PSW bitsM.Balakarthikeyan -

ADD Examplesmov a, #3Fhadd a, #D3h0011 11111101 00110001 0010C = 1AC = 1OV = 0 What is the value ofthe C, AC, OV flagsafter the secondinstruction isexecuted?M.Balakarthikeyan -

Signed Addition and Overflow2’s complement:0000 0000 00 0…0111 1111 7F 1271000 0000 80 -128…1111 1111 FF -10111 1111 (positive 127)0111 0011 (positive 115)1111 0010 (overflowcannot represent 242 in 8bits 2’s complement)1000 1111 (negative 113)1101 0011 (negative 45)0110 0010 (overflow)0011 1111 (positive)1101 0011 (negative)0001 0010 (never overflows)M.Balakarthikeyan -

Addition Example; Computes Z = X + Y; Adds values at locations 78h and 79h and puts them in 7Ah;­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­X equ 78hY equ 79hZ equ 7Ah;­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­org00hljmp Main;­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­org100hMain:mov a, Xadd a, Ymov Z, aendM.Balakarthikeyan -

The 16­bit ADD example; Computes Z = X + Y (X,Y,Z are 16 bit);­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­X equ 78hY equ 7AhZ equ 7Ch;­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­org00hljmp Main;­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­org100hMain:mov a, Xadd a, Ymov Z, amov a, X+1adc a, Y+1mov Z+1, aendM.Balakarthikeyan -

SubtractSUBB A, bytesubtract with borrowExample:SUBB A, #0x4F;A A – 4F – CNotice thatThere is no subtraction WITHOUT borrow.Therefore, if a subtraction without borrow is desired,it is necessary to clear the C flag.Example:Clr cSUBB A, #0x4F;A A – 4FM.Balakarthikeyan -

Increment and DecrementINC AINC byteINC DPTRDEC ADEC byteincrement Aincrement byte in memoryincrement data pointerdecrement accumulatordecrement byte The increment and decrement instructions do NOT affect the Cflag. Notice we can only INCREMENT the data pointer, not decrement.M.Balakarthikeyan -

Example: Increment 16­bit Word Assume 16­bit word in R3:R2mov a, r2add a, #1; use add rather than increment to affect Cmov r2, amov a, r3addc a, #0; add C to most significant bytemov r3, aM.Balakarthikeyan -

MultiplyWhen multiplying two 8­bit numbers, the size ofthe maximum product is 16­bitsFF x FF = FE01(255 x 255 = 65025)MUL AB ; BA A * BNote : B gets the High byteA gets the Low byteM.Balakarthikeyan -

Division Integer DivisionDIV AB ; divide A by BA Quotient(A/B)B Remainder(A/B)OV ­ used to indicate a divide by zero condition.C – set to zeroM.Balakarthikeyan -

Decimal AdjustDA a; decimal adjust aUsed to facilitate BCD addition.Adds “6” to either high or low nibble after an additionto create a valid BCD number.Example:mov a, #23hmov b, #29hadd a, b ; a 23h + 29h = 4Ch (wanted 52)DA a ; a a + 6 = 52M.Balakarthikeyan -

Logic InstructionsBitwise logic operations (AND, OR, XOR, NOT)ClearRotateSwapLogic instructions do NOT affect the flags in PSWM.Balakarthikeyan -

Bitwise LogicANL ANDORL ORXRL XORCPL ComplementExamples:ANLORL000011111010110000001100000011111010110010101111XRLCPL0000111110101100101000111010110001010011M.Balakarthikeyan -

Address Modes with LogicANL – ANDORL – ORXRL – eXclusive oRa, bytedirect, reg. indirect, reg,immediatebyte, adirectCPL – Complementbyte, #constanta ex: cpl aM.Balakarthikeyan -

Uses of Logic Instructions Force individual bits low, without affecting other bits.anl PSW, #0xE7 ;PSW AND 11100111 Force individual bits high.orl PSW, #0x18 ;PSW OR 00011000 Complement individual bitsxrl P1, #0x40 ;P1 XRL 01000000M.Balakarthikeyan -

Other Logic InstructionsCLR - clearRL – rotate leftRLC – rotate left through CarryRR – rotate rightRRC – rotate right through CarrySWAP – swap accumulator nibblesM.Balakarthikeyan -

CLR ( Set all bits to 0)CLR ACLR byteCLR RiCLR @Ri(direct mode)(register mode)(register indirect mode)M.Balakarthikeyan -

Rotate Rotate instructions operate only on aRL aMov a,#0xF0 ; a 11110000RR a ; a 11100001RR aMov a,#0xF0 ; a 11110000RR a ; a 01111000M.Balakarthikeyan -

Rotate through CarryRRC aCmov a, #0A9h; a A9add a, #14h ; a BD (10111101), C0rrc a ; a 01011110, C1RLC aCmov a, #3ch ; a 3ch(00111100)setb c ; c 1rlc a ; a 01111001, C1M.Balakarthikeyan -

Rotate and Multiplication/Division Note that a shift left is the same as multiplyingby 2, shift right is divide by 2mov a, #3 ; A 00000011 (3)clr C ; C 0rlc a ; A 00000110 (6)rlc a ; A 00001100 (12)rrc a ; A 00000110 (6)M.Balakarthikeyan -

SwapSWAP amov a, #72h ; a 27hswap a; a 27hM.Balakarthikeyan -

Bit Logic Operations Some logic operations can be used with single bit operandsANL C, bitORL C, bitCLR CCLR bitCPL CCPL bitSETB CSETB bit “bit” can be any of the bit­addressable RAM locations or SFRs.M.Balakarthikeyan -

Program Flow Control Unconditional jumps (“go to”) Conditional jumps Call and returnM.Balakarthikeyan -

Unconditional Jumps; Short jump,relative address is 8-bit 2’s complementnumber, so jump can be up to 127 locationsforward, or 128 locations back. SJMP LJMP ; Long jump AJMP ; Absolute jump toanywhere within 2K block of program memory JMP @A + DPTRjump; Long indexedM.Balakarthikeyan -

Infinite LoopsStart: mov C, p3.7mov p1.6, Csjmp StartMicrocontroller application programs are almost always infinite loops!M.Balakarthikeyan -

Re-locatable CodeMemory specific NOT Re­locatable (machine code)org 8000hStart: mov C, p1.6mov p3.7, Cljmp StartendRe­locatable (machine code)org 8000hStart: mov C, p1.6mov p3.7, Csjmp StartendM.Balakarthikeyan -

Jump tableMov dptr,#jump_tableMov a,#index_numberRl aJmp @a+dptr...Jump_table: ajmp case0ajmp case1ajmp case2ajmp case3M.Balakarthikeyan -

Conditional Jump These instructions cause a jump to occur only if a condition istrue. Otherwise, program execution continues with the nextinstruction.loop: mov a, P1jz loop ; if a=0, goto loop, ;else goto next instructionmov b, a There is no zero flag (z) Content of A checked for zero on timeM.Balakarthikeyan -

Conditional jumpsMnemonicDescriptionJZ Jump if a = 0JNZ Jump if a != 0JC Jump if C = 1JNC Jump if C != 1JB , Jump if bit = 1JNB , Jump if bit != 1JBC , CJNE A, direct, Jump if bit =1, &clearbitCompare A and memory,jump if not equalM.Balakarthikeyan -

Example: Conditional Jumpsif (a = 0) is truesend a 0 to LEDelsesend a 1 to LEDjz led_offSetb P1.6sjmp skipoverled_off: clr P1.6mov A, P0skipover:M.Balakarthikeyan -

More Conditional JumpsMnemonicCJNE A, #data CJNE Rn, #data CJNE @Rn, #data DJNZ Rn, DJNZ direct, DescriptionCompare A and data, jumpif not equalCompare Rn and data,jump if not equalCompare Rn and memory,jump if not equalDecrement Rn and thenjump if not zeroDecrement memory andthen jump if not zeroM.Balakarthikeyan -

Iterative LoopsFor A = 0 to 4 do{…}For A = 4 to 0 do{…}clr aloop: ......inc acjne a, #4, looploop: ...mov R0, #4...djnz R0, loopM.Balakarthikeyan -

Iterative Loops(examples)mov a,#50hmov b,#00hcjne a,#50h,nextmov b,#01hnext: nopendmov a,#0aahmov b,#10hBack1:mov r6,#50Back2:cpl adjnz r6,back2djnz b,back1endmov a,#25hmov r0,#10hmov r2,#5Again: mov @ro,ainc r0djnz r2,againendmov a,#0hmov r4,#12hBack: add a,#05djnz r4,backmov r5,aendM.Balakarthikeyan -

Call and Return Call is similar to a jump, but Call pushes PC on stack before branchingacall ; stack PC; PC address 11 bitlcall ; stack PC; PC address 16 bitM.Balakarthikeyan -

Return Return is also similar to a jump, but Return instruction pops PC from stack to get addressto jump toret; PC stackM.Balakarthikeyan -

Subroutinescall to the subroutineMain: ...acall sublabel......sublabel: ...the subroutine...retM.Balakarthikeyan -

Initializing Stack Pointer SP is initialized to 07 after reset.(Same address as R7) With each push operation 1st , pc is increased When using subroutines, the stack will be used to store thePC, so it is very important to initialize the stack pointer.Location 2Fh is often used.mov SP, #2FhM.Balakarthikeyan -

Subroutine - Examplesquare: push bmov b,amul abpop bret 8 byte and 11 machine cyclesquare: inc amovc a,@a+pcrettable: db 0,1,4,9,16,25,36,49,64,81 13 byte and 5 machine cycleM.Balakarthikeyan -

Subroutine – another example; Program to compute square root of value on Port 3; (bits 3-0) and output on Port 1.org 0ljmp Mainreset serviceMain: mov P3, #0xFF ; Port 3 is an inputloop:mov a, P3anl a, #0x0F ; Clear bits 7..4 of Alcall sqrtmov P1, amain programsjmp loopsqrt:inc amovc a, @a + PCretsubroutineSqrs: db 0,1,1,1,2,2,2,2,2,3,3,3,3,3,3,3enddataM.Balakarthikeyan -

Why Subroutines? Subroutines allow us to have "structured"assembly language programs. This is useful for breaking a large design intomanageable parts. It saves code space when subroutines can becalled many times in the same program.M.Balakarthikeyan -

example of delaymov a,#0aahBack1:mov p0,alcall delay1cpl asjmp back1Delay1:mov r0,#0ffh;1cycleHere: djnz r0,here ;2cycleret ;2cycleendDelay2:mov r6,#0ffhback1: mov r7,#0ffh ;1cycleHere: djnz r7,here ;2cycledjnz r6,back1;2cycleret;2cycleendDelay=1+(1+255*2+2)*255+2=130818 machine cycleDelay=1+255*2+2=513 cycleM.Balakarthikeyan -

Long delay ExampleGREEN_LED: equ P1.6org oohljmp Mainreset serviceorg 100hMain: clr GREEN_LEDAgain: acall Delaymain programcplGREEN_LEDsjmp AgainDelay: mov R7, #02Loop1: mov R6, #00hLoop0: mov R5, #00hsubroutinedjnz R5, $djnz R6, Loop0djnz R7, Loop1retENDM.Balakarthikeyan -

Example; Move string from code memory to RAMorg 0mov dptr,#stringmov r0,#10hLoop1: clr amovc a,@a+dptrjz stopmov @r0,ainc dptrinc r0sjmp loop1Stop: sjmp stop; on-chip code memory used for stringorg 18hString:endM.Balakarthikeyan -db ‘this is a string’,0

Example; p0:input p1:outputmov a,#0ffhmov p0,aback: mov a,p0mov p1,asjmp backsetb p1.2mov a,#45hAgain:mov p0,asetb p2.3clr p2.3M.Balakarthikeyan -;datajnb p1.2,again ;wait for data request;enable strobe

Example; duty cycle 50%back: cpl p1.2acall delaysjmp backback: setb p1.2acall delayClr p1.2acall delaysjmp backM.Balakarthikeyan -

Example; duty cycle 66%back: setb p1.2acall delayacall delayClr p1.2acall delaysjmp backM.Balakarthikeyan -

M.Balakarthikeyan -8051 timer

Program ExecutionInterrupts…mov a, #2mov b, #16mul abmov R0, amov R1, bmov a, #12mov b, #20mul abadd a, R0mov R0, amov a, R1addc a, bmov R1, aendinterruptreturnISR: inc r7mov a,r7jnz NEXTcpl P1.6NEXT: retiM.Balakarthikeyan -

Interrupt Sources Original 8051 has 5 sources of interrupts Timer 0 overflow Timer 1 overflow External Interrupt 0 External Interrupt 1 Serial Port events (buffer full, buffer empty, etc) Enhanced version has 22 sources More timers, programmable counter array, ADC, more externalinterrupts, another serial port (UART)M.Balakarthikeyan -

Interrupt ProcessIf interrupt event occurs AND interrupt flag forthat event is enabled, AND interrupts areenabled, then:1. Current PC is pushed on stack.2. Program execution continues at the interruptvector address for that interrupt.3. When a RETI instruction is encountered, thePC is popped from the stack and programexecution resumes where it left off.M.Balakarthikeyan -

Interrupt Priorities What if two interrupt sources interrupt at thesame time? The interrupt with the highest PRIORITY getsserviced first. All interrupts have a default priority order. Priority can also be set to “high” or “low”.M.Balakarthikeyan -

Interrupt SFRsGlobal InterruptEnable – must be setto 1 for any interruptto be enabledInterrupt enables for the 5 original 8051 interrupts:Timer 2Serial (UART0)Timer 1External 1Timer 01 = EnableExternal 00 = DisableM.Balakarthikeyan -

Interrupt VectorsEach interrupt has a specific place in code memory whereprogram execution (interrupt service routine) begins.External Interrupt 0:Timer 0 overflow:0003h000BhExternal Interrupt 1: 0013hTimer 1 overflow: 001BhSerial :0023hTimer 2 overflow(8052+) 002bhNote: that thereare only 8memorylocationsbetween vectors.M.Balakarthikeyan -

Interrupt VectorsTo avoid overlapping Interrupt Service routines, it is commonto put JUMP instructions at the vector address. This is similarto the reset vector.org 009B; at EX7 vectorljmp EX7ISRcseg at 0x100; at Main programMain: ...; Main program...EX7ISR:...; Interrupt service routine... ; Can go after main programreti; and subroutines.M.Balakarthikeyan -

Example Interrupt Service Routine;EX7 ISR to blink the LED 5 times.;Modifies R0, R5-R7, bank 3.;----------------------------------------------------ISRBLK: push PSW ;save state of status wordmov PSW,#18h ;select register bank 3mov R0, #10 ;initialize counterLoop2: mov R7, #02h ;delay a whileLoop1: mov R6, #00hLoop0: mov R5, #00hdjnz R5, $djnz R6, Loop0djnz R7, Loop1cpl P1.6 ;complement LED valuedjnz R0, Loop2 ;go on then off 10 timespop PSWretiM.Balakarthikeyan -