214-Pin Micro-DIMM-DDR2-SDRAM Modules MDIMM DDR2 ... - UBiio

Internet Data SheetHYS64T[32/64]0[0/2]0HM–[3S/3.7/5]–AMicro-DIMM DDR2 SDRAM ModulesParameter Symbol Note1)2)3)4)5)Self-Refresh CurrentCKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Databus inputs are FLOATING. I DD6 current values are guaranteed up to T CASE of 85 °C max.All Bank Interleave Read CurrentAll banks are being interleaved at minimum t RC without violating t RRD using a burst length of 4. Controland address bus inputs are STABLE during DESELECTS. I out = 0 mA.I DD6I DD76)1) V DDQ = 1.8 V ± 0.1 V; V DD = 1.8 V ± 0.1 V2) I DD specifications are tested after the device is properly initialized and I DD parameter are specified with ODT disabled.3) Definitions for I DD see Table 194) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode I DD2P5) For details and notes see the relevant Qimonda component data sheet6) I DD1 , I DD4R and I DD7 current measurements are defined with the outputs disabled (I OUT = 0 mA). To achieve this on module level the outputbuffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.TABLE 19Definitions for I DDParameter DescriptionLOW V IN ≤ V IL(ac).MAX , HIGH is defined as V IN ≥ V IH(ac).MINSTABLE Inputs are stable at a HIGH or LOW levelFLOATING Inputs are V REF = V DDQ /2SWITCHING Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and controlsignals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQsignals not including mask or strobesRev. 1.11, 2006-11 2903062006-HT1R-Z2PY