Lyapunov-Based Control Scheme for Single-Phase Grid ... - ITM

526 IEEE TRANSACTIONS ON CONTROL SYSTEMS TECHNOLOGY, VOL. 20, NO. 2, MARCH 2012Fig. 6. Experimental prototype schematic circuitry.Fig. 9. Functions implemented in the FPGA.Fig. 7. PV array electrical curves used the experimental tests.Fig. 10. Experimental Test 1.Fig. 8. Experimental prototype block diagram. Here k is a signal proportionalto A , i.e., k =(A )=(A), see Fig. 9.to generate fast changes in the PV array electrical characteristics.The curves programmed in the SAS for the experimentaltests performed are shown in Fig. 7. Due to the solararray simulator low output voltage level (it has a maximumvoltage of 80 V) a transformer was required to connect theGPV inverter prototype to the grid. As it can be seen in Fig. 6all the measurements where done in the low-voltage side ofthe transformer which exhibits a voltage amplitude of 31.4 Vat 50 Hz, and thus the transformer dynamics was not consideredin the model. Thus, for this experiment we considered thelow-voltage side of the transformer as the grid-voltage and measuredthe power factor in this side. In a larger version of thisprototype (with higher PV array’s voltage) the transformer canbe removed. A primary objective pursued when implementingthe controller was to obtain a simple, economical circuit. Thatis why we decided to divide the controller implementation in ananalog and digital stage. The analog stage has been designed to3 Even though we use a medium size, medium cost FPGA, the implementedalgorithm can be easily migrated to a cheaper PLD, e.g., CPLD or similar.Fig. 11. Experimental Test 2.generate the error signals, and , and the derivative of allowinga wider dynamic range than in most digital systems. Therest of the controller was implemented in a hardwired circuit,more specifically, a Xilinx Spartan three field-programmablegate array (FPGA). A hardwired programmable device is normallymore economical and faster than the equivalent microcontrolleror DSP. 3 The output signals of the analog module arethen quantized by means of ADC converters (ADC AD9525 of12 bits and 25 MSPS). The quantized signals are then inputtedto a digital processing stage implemented in a hardwired device,namely a Xilinx Spartan 3 FPGA. The hardwired algorithms implementedin the FPGA operates synchronously with a clock