RTL8029AS Realtek PCI Full-Duplex Ethernet ... - Cornelius-Consult

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<strong>RTL8029AS</strong> PreliminaryAll bits correspond to the bits in the ISR register. POWER UP=all 0s. Setting individual bits will enable thecorresponding interrupts.DCR: Data Configuration Register (0EH; Type=W in Page0, Type=R in Page2)Bit Symbol Description7 - Always 16, 5 FT1, FT0 FIFO threshold select bit 1 and 0.4 ARM Auto-initialize Remote0: Send Packet Command not executed.1: Send Packet Command executed.3 LS Loopback Select0: Loopback mode selected. Bits 1 and 2 of the TCR must also be programmed forLoopback operation.1: Normal Operation2 LAS This bit must be set to zero. NIC only supports dual 16-bit DMA mode.POWER UP =11 BOS Byte Order Select0: MS byte placed on MD15-8 and LS byte on MD7-0. (32xxx,80x86)1: MS byte placed on MD7-0 and LS byte on MD15-8. (680x0)0 WTS Word Transfer Select0: byte-wide DMA transfer1: word-wide DMA transferTCR: Transmit Configuration Register (0DH; Type=W in Page0, Type=R in Page2)Bit Symbol Description7-5 - Always 1.4 OFST Collision Offset Enable.3 ATD Auto Transmit Disable.0: normal operation1: reception of multicast address hashing to bit 62 disables transmitter,reception of multicast address hashing to bit 63 enables transmitter.2, 1 LB1, LB0LB1 LB0 Mode Remark0 0 0 Normal Operation0 1 1 Internal Loopback1 0 2 External Loopback1 1 3 External Loopback0 CRC The NIC CRC logic comprises a CRC generator for transmitter and a CRC checker forreceiver. This bit controls the activity of the CRC logic. If this bit set, CRC isinhibited by transmitter. Otherwise CRC is appended by transmitter.ConditionsCRC Logic ActivitiesCRC Bit Mode CRC Generator CRC Checker0 normal enabled enabled1 normal disabled enabled0 loopback enabled disabled1 loopback disabled enabledLS009.01997.01.1614Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E-MAIL: info@cornelius-consult.de http://www.cornelius-consult.de
<strong>RTL8029AS</strong> PreliminaryTSR: Transmit Status Register (04H; Type=R in Page0)This register indicates the status of a packet transmission.Bit Symbol Description7 OWC Out of Window Collision. It is set when a collision is detected after a slot time(51.2us). Transmissions are rescheduled as in normal collisions.6 CDH CD Heartbeat. The NIC watches for a collision signal (i.e., CD Heartbeat signal)during the first 6.4us of the interframe gap following a transmission. This bit is set ifthe transceiver fails to send this signal.5 - Always 0.4 CRS Carrier Sense lost bit is set when the carrier is lost during transmitting a packet.3 ABT It indicates the NIC aborted the transmission because of excessive collisions.2 COL It indicates the transmission collided with some other station on the network.1 - Always 1.0 PTX This bit indicates the transmission completes with no errors.RCR: Receive Configuration Register (0CH; Type=W in Page0, Type=R in Page2)Bit Symbol Description7, 6 - Always 1.5 MON When monitor mode bit is set, received packets are checked for address match, goodCRC and frame alignment but not buffered to memory. Otherwise, packets will bebuffered to memory.4 PRO If PRO=1, all packets with physical destination address accepted.If PRO=0, physical destination address must match the node address programmed inPAR0-5.3 AM If AM=1, packets with multicast destination address are accepted.If AM=0, packets with multicast destination address are rejected.2 AB If AB=1, packets with broadcast destination address are accepted.If AB=0, packets with broadcast destination address are rejected.1 AR If AR=1, packets with length fewer than 64 bytes are accepted.If AR=0, packets with length fewer than 64 bytes are rejected.0 SEP If SEP=1, packets with receive errors are accepted.If SEP=0, packets with receive errors are rejected.RSR: Receive Status Register (0CH; Type=R in Page0)Bit Symbol Description7 DFR Deferring. Set when a carrier or a collision is detected.6 DIS Receiver Disabled. When the NIC enters the monitor mode, this bit is set andreceiver is disabled. Reset when receiver is enabled after leaving the monitormode.5 PHY PHY bit is set when the received packet has a multicast or broadcast destinationaddress. It is reset when the received packet has a physical destination address.4 MPA Missed Packet bit is set when the incoming packet can not be accepted by NICbecause of a lack of receive buffer or if NIC is in monitor mode. IncrementCNTR2 tally counter.3 - Always 0.2 FAE Frame Alignment Error bit reflects the incoming packet didn't end on a byteboundary and CRC did not match at last byte boundary. Increment CNTR0 tallycounter.1 CRC CRC error bit reflects packet received with CRC error. This bit will also be setfor FAE errors. Increment CNTR1 tally counter.0 PRX This bit indicates packet received with no errors.LS009.01997.01.1615Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E-MAIL: info@cornelius-consult.de http://www.cornelius-consult.de
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RTL8029AS Realtek PCI Full-Duplex Ethernet ... - Cornelius-Consult

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