RTL8029AS Realtek PCI Full-Duplex Ethernet ... - Cornelius-Consult

RTL8029AS Preliminaryq Alignment of the Reception FIFOThe reception FIFO is an 8-byte ring structure. The first received byte is put at location zero. When the locationpointer goes to the end of the FIFO, it wraps to the beginning of the FIFO and overwrites the previous data. At theend of the packet reception, the FIFO contents are in the "order" (from the ring structure's view) as shown below.(1) CRC enabled (CRC bit in TCR=0)s 1-byte received packet datas 4-byte CRCs 1-byte lower byte counts 1-byte upper byte counts 1-byte upper byte count(2) CRC disabled (CRC bit in TCR=1)s 5-byte received packet datas 1-byte lower byte counts 1-byte upper byte counts 1-byte upper byte count6.6.2. To Implement Loopback Test(1) To verify the integrity of data paths set RCR=00H to accept physical packets set PAR0-5 to accept packets set DCR=43Hs set TCR=02H, 04H, 06H to do loopback test 1, 2, 3 respectivelys set CRC enabled (CRC=00H in TCR)s clear ISRs Tx a packet and check ISRs check FIFO after loopbackNotes: Loopback mode 3 is sensitive to the network traffic, so the values of FIFO may be not(2) To verify CRC logicq Select a loopback mode (e.g. mode 2) to testA. To test CRC generators set RCR=00H to accept physical packets set PAR0-5 to accept packets set TCR=04H (CRC enabled)s set DCR=43Hs clear ISRs Tx a packets check CRC bytes in FIFO after loopbackB. To test CRC checkers set RCR=00H to accept physical packets set PAR0-5 to accept packets set TCR=05H (CRC disabled)s set DCR=43Hs clear ISRs Tx a packet with good or bad CRC appended by programs check FIFO, ISR & RSR after loopbackFor bad CRC, expected: ISR=06H, RSR=02H (Tx:OK, Rx:CRC error)For good CRC, expected: ISR=02H, RSR=01H (Tx:OK, Rx:OK)correct.LS009.01997.01.1632Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E-MAIL: info@cornelius-consult.de http://www.cornelius-consult.de