RTL8029AS Realtek PCI Full-Duplex Ethernet ... - Cornelius-Consult

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RTL8029AS Preliminary3. PIN CONFIGURATION66 MA1267 MA1368 LED2[LED_TX]69 LED1[LED_RX][LED_CRS]70 LED0[LED_COL][LED_LINK]71 LED_BNC72 GND73 TPOUT+74 TPOUT-75 VDD76 TX-77 TX+78 X179 X280 GND65 MA1164 MA1063 MA962 MA861 MA760 MA659 MA558 MA457 MA3[EESK]56 MA2[EEDI]55 MA1[EEDO]54 MA053 EECS52 VDD51 MA1481 CD-82 CD+83 RX-84 RX+85 VDD86 TPIN-87 TPIN+88 INTAB89 RSTB90 CLK91 GND92 AD3193 AD3094 AD2995 AD2896 AD2797 AD2698 AD2599 AD24100 VDDRTL8029AS50 NC49 BOEB48 GND47 MD046 MD145 MD244 MD343 MD442 MD541 MD640 MD739 VDD38 AD037 AD136 AD235 AD334 GND33 AD432 AD531 AD61 CBE3B2 IDSEL3 AD234 AD225 AD216 AD207 AD198 AD189 AD1710 AD1611 GND12 CBE2B13 FRAMEB14 IRDYB15 TRDYB30 AD729 CBE0B28 AD827 AD926 AD1025 AD1124 AD1223 AD1322 VDD21 AD1420 AD1519 CBE1B18 PAR17 GND16 DEVSELBLS009.01997.01.166Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E-MAIL: info@cornelius-consult.de http://www.cornelius-consult.de
RTL8029AS Preliminary4. PIN DESCRIPTIONS4.1. Signal Type DefinitionPIOT/SPower pins include VDD and GND.Input is a standard input-only signal.It indicates output signal.Tri-State is a bi-directional, tri-state input/output pin.S/T/S Sustained Tri-State is an active low tri-state signal owned and driven by one and only one agentat a time. The agent that drives an S/T/S pin low must drive it high for at least one clock beforeletting it float.O/D4.2. Power PinsOpen Drain allowed multiple device to share as a wire-OR.No. Name Type Description22, 39, 52, VDD P +5V DC power75, 85, 10011, 17, 34,48, 72, 80,91GND P Ground4.3. PCI Bus Interface PinsNo. Name Type Descriptions90 CLK I Bus Clock provides timing for all transactions on PCI and isan input pin to every PCI device. All bus signals aresampled on the rising edge of CLK and all parameters aredefined with respect to this edge.92-99,3-10, 20,21, 23-28,30-33,35-381, 12, 19,29AD31-0 T/S Address/Data are multiplexed on the same PCI pins. A bustransaction consists of an address phase followed by one ormore data phases. The address phase is the clock cycle inwhich FRAMEB is asserted. During data phase AD7-0contain the least significant byte(lsb) and AD31-24 containthe most significant byte(msb). Write data is stable and validwhen IRDYB is asserted and read data is stable and validwhen TRDYB is asserted.CBE3-0B T/S Bus Command/Byte Enables are multiplexed on the samePCI pins. During the address phase of a transaction,CBE3-0B define the Bus Command. During the data phaseCBE3-0B are used as Byte Enables. The Byte Enablesdefine which physical byte lanes carry meaning data.CBE0B applies to byte 0(lsb) and CBE3B applies to byte3(msb).18 PAR T/S Parity is even parity across AD31-0 and CBE3-0B. PAR isstable and valid one clock after the address phase. For dataphases PAR is stable and valid one clock after either IRDYBis asserted on a write transaction or TRDYB is asserted on aLS009.01997.01.167Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E-MAIL: info@cornelius-consult.de http://www.cornelius-consult.de
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