Non-linear memory layout transformations and data prefetching ...

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xCONTENTS2.7 Iteration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202.8 Data dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202.9 Data Reuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.10 Loop Transformations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Fast Indexing for Blocked Array Layouts 313.1 The problem: Improving cache locality for array computations . . . . . . . . . . 313.2 Morton Order matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.3 Blocked array layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.3.1 The 4D layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.3.2 The Morton layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.3.3 Our approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413.3.4 Mask Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.3.5 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453.3.6 Example : Matrix Multiplication . . . . . . . . . . . . . . . . . . . . . . . 473.3.7 The Algorithm to select the Optimal Layout per Array . . . . . . . . . . 503.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 A Tile Size Selection Analysis 554.1 Theoretical analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564.1.1 Machine and benchmark specications . . . . . . . . . . . . . . . . . . . . 564.1.2 Data L1 misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574.1.3 L2 misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694.1.4 Data TLB misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704.1.5 Mispredicted branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714.1.6 Total miss cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724.2 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 Simultaneous Multithreading 755.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755.2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765.3 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795.4 Quantitative analysis on the TLP and ILP limits of the processor . . . . . . . . 815.4.1 Co-executing streams of the same type . . . . . . . . . . . . . . . . . . . . 815.4.2 Co-executing streams of dierent types . . . . . . . . . . . . . . . . . . . . 825.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 Experimental Results 856.1 Experimental results for Fast Indexing . . . . . . . . . . . . . . . . . . . . . . . . 856.1.1 Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
CONTENTSxi6.1.2 Time Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866.1.3 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916.2 Experimental Results for Tile Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . 936.2.1 Execution Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936.2.2 Experimental verication . . . . . . . . . . . . . . . . . . . . . . . . . . . 956.2.3 MBaLt performance: Tile size selection . . . . . . . . . . . . . . . . . . . 956.2.4 MBaLt vs linear layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956.2.5 More Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976.3 Experimental Framework and Results on SMTs . . . . . . . . . . . . . . . . . . . 996.3.1 Further Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037 Conclusions 1077.1 Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Appendices 109A Table of Symbols 111B Hardware Architecture 113C Program Codes 115C.1 Matrix Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C.2 LU decomposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116C.3 STRMM: Product of Triangular and Square Matrix . . . . . . . . . . . . . . . . 116C.4 SSYMM: Symmetric Matrix-Matrix Operation . . . . . . . . . . . . . . . . . . . 117C.5 SSYR2K: Symmetric Rank 2k Update . . . . . . . . . . . . . . . . . . . . . . . . 118Bibliography 119
Page 1: NATIONAL TECHNICAL UNIVERSITY OF AT
Page 4 and 5: .................Evangelia G. Athan
Page 6 and 7: vióôéò ìç-ãñáììéêÝò
Page 8 and 9: viiiAnother issue, that had not bee
Page 12 and 13: xiiCONTENTS
Page 14 and 15: xivLIST OF FIGURES4.4 Alignment of
Page 16 and 17: xviLIST OF FIGURES
Page 18 and 19: xviiiLIST OF TABLES
Page 20 and 21: äýíáìç ðñïò ôç óõíå
Page 22 and 23: 2 Introductionthe processor die its
Page 24 and 25: 4 Introductionthe instruction strea
Page 26 and 27: 6 IntroductionUnfortunately, the pe
Page 28 and 29: 8 Introduction• A study of the ee
Page 30 and 31: 10 Introduction
Page 32 and 33: 12 Basic ConceptsPart of the On-chi
Page 34 and 35: 14 Basic Conceptsapplication execut
Page 36 and 37: 16 Basic Conceptscache entries, it
Page 38 and 39: 18 Basic Concepts• Least-Recently
Page 40 and 41: 20 Basic Conceptstable. Of course,
Page 42 and 43: 22 Basic ConceptsIn the above examp
Page 44 and 45: 24 Basic Concepts• Forward expres
Page 46 and 47: 26 Basic ConceptsThe following unim
Page 48 and 49: 28 Basic Conceptsfor (i = 0; i
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72 A Tile Size Selection AnalysisTL
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74 A Tile Size Selection Analysis4.
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76 Simultaneous MultithreadingAlong
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78 Simultaneous Multithreadingas be
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80 Simultaneous MultithreadingFor c
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82 Simultaneous Multithreading871th
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84 Simultaneous MultithreadingExami
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86 Experimental Results3500MBalttil
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88 Experimental Results2000MBaLttil
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90 Experimental Results140MBaLtMBaL
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92 Experimental Resultsnumber of mi
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94 Experimental Resultsnumber of mi
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96 Experimental ResultsTotal penalt
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98 Experimental Resultsso that dier
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100 Experimental Results10STRMMSSYR
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102 Experimental ResultsNorm. Perfo
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104 Experimental Resultstool. Figur
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106 Experimental Results
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108 Conclusionsdata are now stored
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APPENDIXATable of SymbolsExplanatio
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APPENDIXBHardware ArchitectureUltra
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APPENDIXCProgram CodesIn the follow
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C.4 SSYMM: Symmetric Matrix-Matrix
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Bibliography[AAKK05]Evangelia Athan
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BIBLIOGRAPHY 121ference on Programm
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BIBLIOGRAPHY 123[KPCM99][KRC97][KRC
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BIBLIOGRAPHY 125[RS01][RT98a][RT98b
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BIBLIOGRAPHY 127[WM95][WMC96]Wm. A.
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