Non-linear memory layout transformations and data prefetching ...

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viiiAnother issue, that had not been thoroughly examined so far, is Simultaneous Multithreading(SMT) for single-program workloads. SMT has been proposed to improve system throughput byoverlapping multiple (either multi-programmed or explicitly parallel) threads on a single wideissueprocessor. Recent studies have demonstrated that heterogeneity of simultaneously executedapplications can bring up signicant performance gains due to SMT. However, the speedup of asingle application that is parallelized into multiple threads, is often sensitive to the eciency ofsynchronization and communication mechanisms between its separate, but possibly dependent,threads. Moreover, as these separate threads tend to put pressure on the same architecturalresources, no signicant speedup can be achieved. This thesis evaluates and contrasts softwareprefetching and thread-level parallelism (TLP) techniques. It also examines the eect of threadsynchronization mechanisms on multithreaded parallel applications that are executed on a singleSMT processor.Keywords: Memory Hierarchy, Loop tiling, Blocked Array Layouts, Binary Masks, Prefetching,Loop Unrolling, Tile Size Selection, Simultaneous Multithreading, Single Program Workload,Resource Release by idle Threads.
ContentsÐåñßëçøçAbstractList of FiguresList of TablesÁíôß Ðñïëüãïõvviixiiixviixix1 Introduction 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 Compiler Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1.2 Non-linear Memory Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . 41.1.3 Tile Size/Shape Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.3 Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.4 Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Basic Concepts 112.1 Memory Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.2 Cache misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.3 Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.3.1 Pseudo-associative caches . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.3.2 Victim Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.3.3 Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.4 Cache replacement policies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.5 Write policies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.6 Virtual Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page 1: NATIONAL TECHNICAL UNIVERSITY OF AT
Page 4 and 5: .................Evangelia G. Athan
Page 6 and 7: vióôéò ìç-ãñáììéêÝò
Page 10 and 11: xCONTENTS2.7 Iteration Space . . .
Page 12 and 13: xiiCONTENTS
Page 14 and 15: xivLIST OF FIGURES4.4 Alignment of
Page 16 and 17: xviLIST OF FIGURES
Page 18 and 19: xviiiLIST OF TABLES
Page 20 and 21: äýíáìç ðñïò ôç óõíå
Page 22 and 23: 2 Introductionthe processor die its
Page 24 and 25: 4 Introductionthe instruction strea
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Page 28 and 29: 8 Introduction• A study of the ee
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Page 48 and 49: 28 Basic Conceptsfor (i = 0; i
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56 A Tile Size Selection Analysis[M
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58 A Tile Size Selection Analysismi
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62 A Tile Size Selection Analysisd.
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64 A Tile Size Selection AnalysisRe
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70 A Tile Size Selection AnalysisWe
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74 A Tile Size Selection Analysis4.
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76 Simultaneous MultithreadingAlong
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78 Simultaneous Multithreadingas be
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80 Simultaneous MultithreadingFor c
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82 Simultaneous Multithreading871th
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84 Simultaneous MultithreadingExami
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86 Experimental Results3500MBalttil
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88 Experimental Results2000MBaLttil
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90 Experimental Results140MBaLtMBaL
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92 Experimental Resultsnumber of mi
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94 Experimental Resultsnumber of mi
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96 Experimental ResultsTotal penalt
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98 Experimental Resultsso that dier
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100 Experimental Results10STRMMSSYR
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102 Experimental ResultsNorm. Perfo
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104 Experimental Resultstool. Figur
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106 Experimental Results
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108 Conclusionsdata are now stored
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APPENDIXATable of SymbolsExplanatio
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APPENDIXBHardware ArchitectureUltra
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APPENDIXCProgram CodesIn the follow
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C.4 SSYMM: Symmetric Matrix-Matrix
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Bibliography[AAKK05]Evangelia Athan
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BIBLIOGRAPHY 121ference on Programm
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BIBLIOGRAPHY 123[KPCM99][KRC97][KRC
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BIBLIOGRAPHY 125[RS01][RT98a][RT98b
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BIBLIOGRAPHY 127[WM95][WMC96]Wm. A.
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