Non-linear memory layout transformations and data prefetching ...

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8 Introduction• A study of the eects of multiple code optimization methods in dierent machines. Thisstudy matches specic optimizations with hardware characteristics, tracking down weaknessesthat can be healed when pipeline is being fed by an appropriate stream of instructions.1.3 Thesis OverviewThis work is organized as follows:Chapter 2 gives some background about memory hierarchy organization and basic cachememory characteristics. We present the terminology of code optimization techniques used inthis work. Finally, we provide an introduction about loop tiling and transformations.Chapter 3 presents the underlying model on which this work is based, that is pre-existingnon-linear array layouts. Then, the proposed blocked array layouts are analytically described,combined with a fast indexing scheme. A system of binary masks has been developed, which isused to pick up data elements of multidimensional arrays in the one dimensional storage order.Chapter 4 analyzes the cache behavior when tiled codes with blocked array layouts are beingexecuted. The best tile size that utilizes the cache capacity and deters conict misses is beingcalculated as the convergence point of all factors (cache misses and latency of multiple cachelevels and TLBs, and branch miss penalty) that aect cache performance.Chapter 5 outlines the framework of Simultaneous Multithreading (SMT) micro-architectureand discusses implementation and synchronization issues. It also explores the performancelimits of simultaneously executed instruction streams, using homogeneous instruction streams,executed in parallel.Chapter 6 presents experimental and simulation results on various platforms, evaluatingblocked array layouts versus other non-linear array layouts, the tile selection technique and theperformance of Simultaneous Multithreading on optimized codes.Finally, chapter 7 gives the conclusion remarks.1.4 PublicationsINTERNATIONAL CONFERENCES• Evangelia Athanasaki, Nikos Anastopoulos, Kornilios Kourtis and Nectarios Koziris. Exploringthe Capacity of a Modern SMT Architecture to Deliver High Scientic ApplicationPerformance. In Proc. of the 2006 International Conference on High Performance Computingand Communications (HPCC-06), pages , Munich, Germany, Sep 2006. LectureNotes in Computer Science.
1.4 Publications 9• Evangelia Athanasaki, Nikos Anastopoulos, Kornilios Kourtis and Nectarios Koziris. Exploringthe Performance Limits of Simultaneous Multithreading for Scientic Codes. InProc. of the 2006 International Conference on Parallel Processsing (ICPP-06), pages ,Columbus, OH, Aug 2006. IEEE Computer Society Press.• Evangelia Athanasaki, Nikos Anastopoulos, Kornilios Kourtis and Nectarios Koziris. TuningBlocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures. In Proc.of the 10th Panhellenic Conference in Informatics, pages , Volos, Greece, Nov 2005. LectureNotes in Computer Science.• Evangelia Athanasaki, Nectarios Koziris and Panayiotis Tsanakas. A Tile Size SelectionAnalysis for Blocked Array Layouts. In Proc. of the 9-th Workshop on Interactionbetween Compilers and Computer Architectures (INTERACT-9), In conjuction with the11th International Symposium on High-Performance Computer Architecture (HPCA-11),pages 70{80, San Francisco, CA, Feb 2005. IEEE Computer Society Press.• Evangelia Athanasaki and Nectarios Koziris. Fast Indexing for Blocked Array Layoutsto Improve Multi-Level Cache Locality. In Proc. of the 8-th Workshop on Interactionbetween Compilers and Computer Architectures (INTERACT-8), In conjuction with the10th International Symposium on High-Performance Computer Architecture (HPCA-10),pages 109{119, Madrid, Spain, Feb 2004. IEEE Computer Society Press.• Evangelia Athanasaki and Nectarios Koziris. Improving Cache Locality with BlockedArray Layouts. In Proceedings of the 12-th Euromicro Conference on Parallel, Distributedand Network based Processing (PDP'04), pages 308{317, A Coruna, Spain, Feb. 2004.IEEE Computer Society Press.• Evangelia Athanasaki and Nectarios Koziris. Blocked Array Layouts for Multilevel MemoryHierarchies. In Proceedings of the 9th Panhellenic Conference in Informatics, pages193{207, Thessaloniki, Greece, Nov. 2003.INTERNATIONAL JOURNALS• Evangelia Athanasaki and Nectarios Koziris. Fast Indexing for Blocked Array Layoutsto Reduce Cache Misses. International Journal of High Performance Computing andNetworking (IJHPCN), 3(5/6): 417{433, 2005.• Evangelia Athanasaki, Nikos Anastopoulos, Kornilios Kourtis and Nectarios Koziris. Exploringthe Performance Limits of Simultaneous Multithreading for Memory IntensiveApplications. The Journal of Supercomputing, submitted.
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90 Experimental Results140MBaLtMBaL
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108 Conclusionsdata are now stored
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APPENDIXATable of SymbolsExplanatio
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APPENDIXBHardware ArchitectureUltra
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APPENDIXCProgram CodesIn the follow
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C.4 SSYMM: Symmetric Matrix-Matrix
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Bibliography[AAKK05]Evangelia Athan
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BIBLIOGRAPHY 121ference on Programm
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BIBLIOGRAPHY 123[KPCM99][KRC97][KRC
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BIBLIOGRAPHY 125[RS01][RT98a][RT98b
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BIBLIOGRAPHY 127[WM95][WMC96]Wm. A.
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