Non-linear memory layout transformations and data prefetching ...

List of Tables3.1 Indexing of array dimensions, in the matrix multiplication code, when loops arenested in (ii, jj, kk, i, j, k) order : C[i, j]+ = A[i, k] ∗ B[k, j] . . . . . . . . . . . 494.1 Calculation formulas for direct-mapped L1 cache misses . . . . . . . . . . . . . . 654.2 Formulas for set associative Data L1 misses . . . . . . . . . . . . . . . . . . . . . 684.3 Formulas for Data TLB misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715.1 Hardware management in Intel hyper-threaded processors . . . . . . . . . . . . . 785.2 Average CPI for dierent TLP and ILP execution modes of some common instructionstreams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815.3 Slowdown factors from the co-execution of various instruction streams . . . . . . 836.1 Processor subunits utilization from the viewpoint of a specic thread . . . . . . 104A.1 Table of Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111B.1 Table of machine characteristics, used for experimentation . . . . . . . . . . . . . 113B.2 Table of machine characteristics, used for experimentation . . . . . . . . . . . . . 114