Non-linear memory layout transformations and data prefetching ...

2.3 Cache Organization 15processor clocks favor this organization for st-level caches, that should be kept small insize.• Fully Associative cache: A given block of memory elements can reside anywhere in cache.This mapping reduces miss rate because it eliminates conict misses. Of course, increasedassociativity comes at a cost. This is the increase of hit time and the high structuralcost. However, even if fast processor clocks favor simple caches for on-chip caches, as wedraw away from processor chip to higher-level caches, increasing of miss penalty rewardsassociativity.• N-way Set Associative cache: A set associative organization denes that cache is dividedinto sets of N cache lines. A given block of memory can be placed anywhere within a singleset. This set is determined by the block address:(set mapped) = (Block address) MOD (Number of sets in cache)A direct mapped cache can be considered as an 1-way set associative cache, while a fully associativecache with capacity of M cache lines can be considered as a M-way set associativecache.As far as cache performance is considered, an 8-way set associative cache has, in essence,the same miss rate as a fully associative cache.2.3.1 Pseudo-associative cachesAnother approach to improve miss rates without aecting the processor clock is pseudo-associativecaches. This mechanism is so eective as 2-way associativity. Pseudo-associative caches thenhave one fast and one slow hit time -corresponding to a regular hit and a pseudo hit. On a hit,pseudo-associative caches work just like direct mapped caches. When a miss occurs in the directmapped entry, an alternate entry (the index with the highest index bit ipped) is checked. A hitto the alternate entry (pseudo-hit) requires an extra cycle. This pseudo-hit results in the twoentries being swapped, so that the next access to the same line would be a fast access. A missin both entries (fast and alternative) causes an eviction of whichever of the two lines is LRU.The new data is always placed in the fast index, so if the alternate index was evicted, the linein the fast index will need to be moved to the alternate index. So a regular hit takes no extracycles, a pseudo-hit takes 1 cycle, and access to the L2 and main memory takes 1 cycle longerin a system with a pseudo-associative cache than in one without.2.3.2 Victim CachesCache conicts can be addressed in the hardware through associativity of some form. Whileassociativity has the advantage of reducing conicts by allowing locations to map to multiple