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Product SpecificationLow Cost Green-Mode PWM Controller for Flyback ConvertersSG6848OPERATION DESCRIPTIONSG6848 devices integrate many useful designs intoone controller for low-power switch-mode power supplies.The following descriptions highlight some of the featuresof the SG6848 series.Start-up CurrentThe start-up current is only 5uA. Low start-upcurrent allows a start-up resistor with a high resistanceand a low-wattage to supply the start-up power for thecontroller. A 1.5 MΩ, 0.25W, start-up resistor and a10uF/25V V DD hold-up capacitor would be sufficient foran AC-to-DC power adapter with a wide input range(100V AC to 240V AC ).Operating CurrentThe operating current has been reduced to 2mA. Thelow operating current results in higher efficiency andreduces the V cc hold-up capacitance requirement.Green-Mode OperationThe proprietary green-mode function providesoff-time modulation to linearly decrease the switchingfrequency under light-load conditions. On-time is limitedto provide stronger protection against brownouts andother abnormal conditions. The feedback current, which issampled from the voltage feedback loop, is taken as thereference. Once the feedback current exceeds thethreshold current, the switching frequency starts todecrease. This green-mode function dramatically reducespower consumption under light-load and zero-loadconditions. Power supplies using the SG6848 can easilymeet even the strictest regulations regarding standbypower consumption.Oscillator OperationA resistor connected from the RI pin to ground willgenerate a constant current source for the SG6848. Thiscurrent is used to charge an internal capacitor. Thecharge-time determines the internal clock speed and theswitching frequency. Increasing the resistance will reducethe amplitude of the input current and reduce theswitching frequency. A 95kΩ resistor R i results in a 50uAconstant current I i and a 70kHz switching frequency. Therelationship between R i and the switching frequency is:fPWM6650= (kHz )RI(kΩ)The range of the oscillation frequency is designed tobe within 50kHz ~ 100kHz.Leading-Edge BlankingEach time the power MOSFET is switched on, aturn-on spike will inevitably occur at the sense-resistor.To avoid premature termination of the switching pulse, a250 nsec leading-edge blanking time is built in.Conventional RC filtering can therefore be omitted.During this blanking period, the current-limit comparatoris disabled and it cannot switch off the gate driver.Constant Output Power LimitWhen the SENSE voltage across the sense resistor R sreaches the threshold voltage (around 1.0V), the outputGATE drive will be turned off following a shortpropagation delay t D . This propagation delay willintroduce an additional current proportional to t D *V in /L p .The propagation delay is nearly constant regardless of theinput line voltage V IN . Higher input line voltages willresult in larger additional currents. At high input linevoltages, the output power limit will be higher than at lowinput line voltages.To compensate for this output power limit variationacross a wide AC input range, the threshold voltage isadjusted by adding a positive ramp. This ramp signal risesfrom 0.85V to 1.0V, and then flattens out at 1.0V. Asmaller threshold voltage forces the output GATE drive toterminate earlier. This reduces the total PWM turn-ontime and makes the output power equal to that of low lineinput. This proprietary internal compensation ensures aconstant output power limit for a wide AC input voltagerange (90VAC to 264VAC).© System General Corp. - 8 - www.sg.com.twVersion 1.2(IRO33.0010.B0) May.06, 2003
Product SpecificationLow Cost Green-Mode PWM Controller for Flyback ConvertersSG6848Under Voltage Lockout (UVLO)The turn-on and turn-off thresholds of the SG6848are fixed internally at 16.3V/11.7V. During start-up, thehold-up capacitor must be charged to 16.3V through thestart-up resistor, so that the SG6848 will be enabled. Thehold-up capacitor will continue to supply V DD until powercan be delivered from the auxiliary winding of the maintransformer. V DD must not drop below 11.7V during thisstart-up process. This UVLO hysteresis window ensuresthat hold-up capacitor will be adequate to supply V DDduring start-up.Gate OutputThe SG6848 BiCMOS output stage is a fast totempole gate driver. Cross conduction has been avoided tominimize heat dissipation, increase efficiency, andenhance reliability. The output driver is clamped by aninternal 15V Zener diode in order to protect powerMOSFET transistors against undesired over-voltage gatesignals.Built-in Slope CompensationThe sensed voltage across the current sense resistoris used for current mode control and pulse-by-pulsecurrent limiting. Built-in slope compensation willimprove stability and prevent sub-harmonic oscillationsdue to peak-current mode control. The SG6848 has asynchronized, positively-sloped ramp built-in at eachswitching cycle. The slope of the ramp is:0.33× DutyDuty(max)Noise ImmunityNoise from the current sense or the control signal cancause significant pulse width jitter, particularly incontinuous-conduction mode. While slope compensationhelps alleviate these problems, further precautions shouldstill be taken. Good placement and layout practices shouldbe followed. Avoiding long PCB traces and componentleads, locating compensation and filter components nearthe SG6848, and increasing the power MOS gateresistance is advised.© System General Corp. - 9 - www.sg.com.twVersion 1.2(IRO33.0010.B0) May.06, 2003
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