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LTR Recommendation for Server DevicesDevices LTR_Active LTR_Act_Idle LTR_Idle CommentsEthernet LAN(1Gb orlower)60usec300usec(minimum)LTR_MaxPlatLat(LPI mode)Device Initiated≥10 Gb(Ethernet,FibreChannel,orInfiniBand)50usecOptional in 1 st genplatformsLTR_MaxPlatLat(LPI mode)Device InitiatedSATAControllerSASController50usec Optional LTR_MaxPlatLat Can be SW guided50usec Optional LTR_MaxPlatLat Can be SW guidedAny LTR value below 50usec will result in increased platform power• Request lower values only when performance is needed – for short durations• These numbers are preliminary. Monitor the following link for updates:http://developer.intel.com/technology/pciexpress/devnet/index.htm18
Use of Device Buffer WatermarksExample: Buffer Flushes for Receive Path on NIC• On-chip buffers must be flushed whenthe “high-water mark” (HWM) is hitto prevent over-runs– Defined down from the top of the buffer byat least LTR + the PCIe L1 exit latency• Depending on application, bufferslikely will be flushed based on varioustime-out situations– For example, preventing “stale” data• “Low-water marks” (LWM) arerecommended to coalesce data formore efficient bus usage– LWM effectively sets a minimum size for atransmission (to host) blockHWMLWMRx Bufferreceive data(from network)LTR + L1 Exit:flush to avoidoverrun19
Page 1 and 2: Device Guidelines for PCIExpress* T
Page 3: Agenda• Impact of devices on plat
Page 6 and 7: Agenda• Impact of devices on plat
Page 8 and 9: Latency Tolerance Reporting (LTR)Ac
Page 10 and 11: LTR - Device ImplementationOS Bus D
Page 12 and 13: Optimized Buffer Flush/Fill (OBFF)O
Page 14 and 15: Active State Power Management (ASPM
Page 16 and 17: LTR Recommendation for Client Devic
Page 20 and 21: Implementation Guidelines for OBFFE
Page 22 and 23: Summary• Impact of devices (even
Page 24 and 25: Next Steps• Download the PCI Expr
Page 26 and 27: Legal Disclaimer• INFORMATION IN
Page 28 and 29: 28Backup Slides
Page 30 and 31: Example: WLAN DeviceLTR_Active_Idle

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