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Use of Device Buffer WatermarksExample: Buffer Flushes for Receive Path on NIC• On-chip buffers must be flushed whenthe “high-water mark” (HWM) is hitto prevent over-runs– Defined down from the top of the buffer byat least LTR + the PCIe L1 exit latency• Depending on application, bufferslikely will be flushed based on varioustime-out situations– For example, preventing “stale” data• “Low-water marks” (LWM) arerecommended to coalesce data formore efficient bus usage– LWM effectively sets a minimum size for atransmission (to host) blockHWMLWMRx Bufferreceive data(from network)LTR + L1 Exit:flush to avoidoverrun19