Migrating from PowerQUICC II Pro to QorIQ's P1010 - Freescale

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• Power-on reset sequence is significantly different to PowerQUICC II Pro family − HRESET# —now input only and replaces PORESET# input − HRESET_REQ# —output, used to request reset − SRESET# —input only − READY_P0 / TRIG_OUT —Core 0 ready output / external trigger output − READY_P1 —Core 1 ready output (if available) • Signals no longer available − CFG_RESET_SOURCE[0:3] —used to load configuration words; function replaced by POR configuration pins − CFG_CLKIN_DIV# —clock division selection is carried out by POR PLL config pins TM 36 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.
Stable SYSCLK Signal Stable PLL Configuration Input POR Configuration Input TM 37 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.
Page 1 and 2: January 2012 TM Freescale, the Free
Page 3 and 4: • Introduction to P1010 QorIQ Pla
Page 5 and 6: Performance & Power PowerQUICC II P
Page 7 and 8: • New IPs/blocks − Integrated F
Page 9 and 10: • Up to 1.2 GHz (800 MHz in P1010
Page 11 and 12: • DDR memory controller − DDR3
Page 13 and 14: •eTSEC MAC controllers support 10
Page 15 and 16: • Dual SATA 3 Gbps controllers wi
Page 17 and 18: • Pin multiplexing is available b
Page 19 and 20: • SerDes I/O port multiplexing (t
Page 21 and 22: • USB 2.0 host and device control
Page 23: • Power sequencing is different f
Page 26 and 27: • P1/P2 platforms have power on r
Page 28 and 29: • DDR3 guidelines available from
Page 30 and 31: Following applies for both PowerQUI
Page 32 and 33: TM Freescale, the Freescale logo, A
Page 36 and 37: TM 38 • Supports DDR asynchronous
Page 38 and 39: TM Freescale, the Freescale logo, A
Page 40 and 41: • Power Architecture cores operat
Page 42 and 43: e500v2 BBEAR BBTAR BUCSR L1 Cache L
Page 44 and 45: Main Program TM PC → SRR0 MSR →
Page 46 and 47: e500v2 Translations Address Space |
Page 48 and 49: • Integer arithmetic, compare, lo
Page 50 and 51: • Processor control − All move
Page 52 and 53: Reset Branch to FFFFF000 Invalidate
Page 54 and 55: Operating Systems, Software IDE, Co
Page 56 and 57: To LAN To WAN PHY PHY PHY PHY PHY G
Page 58 and 59: To LAN WiFi • e300 based platform
Page 60 and 61: ►New board design required for Qo
Page 62: ►Migration from e300 to e500 base
Page 65 and 66: Interrupt Type e300 e500 System res
Page 67 and 68: • After reset, by default, the fi
Page 69 and 70: • AS=0 -> AS=1 /* create a temp m
Page 71 and 72: Mnemonic e300 e500 eieio √ Replac

Migrating from PowerQUICC II Pro to QorIQ's P1010 - Freescale

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