Introducing QorIQ P3041 Processor - Freescale

Introducing QorIQ P3041 Processor 

FTF-NET-F0874 

Katie Eckermann 

Networking Segment Marketing 

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., 

Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink 

and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 

TM

• Market Trends 

• Introducing the QorIQ P3041 Processor 

• QorIQ P3041 Accelerators Overview 

• Application Use Cases and Ecosystem 

• Summary 



and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 2 

Agenda 

TM

SMART, CONNECTED … 

Mobile devices 

Enterprise/Cloud Computing 

Medical Devices 

Car, Transport 

Grid, Home 

Human collaboration 

Machine 2 machine 

Cloud Based Services 

Smart Networks 

Wireless & Wired 




The Evolving Network 

Enterprise & 

SMB 

3 

Consumer, 

Residential 

Industrial, 

Mil/Aero 

Tablets 

eReaders 

Smartbooks 

Infotainment/ 

Telematics 

Factory HMI 

Energy 

Gateways 

Mobile Internet 

Device 

Touch Screen 

Printers 

10B (to 50B) mobile 

connected devices by 2020? 

Smart, Efficient Networking Backbone for Trusted Connections 

TM

IP Traffic Growth 

(Relative to 2008=1) 

The Gap 

“The Gap” 

Exponentially increasing performance 

demands cannot be met by 

Moore’s Law alone. 

Explosion of traffic with flatting of CapEx is 

driving consolidation & higher efficiency in 

network infrastructure. 

Source: Cisco, June 2009 




Network Explosion Trends 

Elements of Global IP Traffic 

Control & Data plane applications need higher 

performance to respond to IP traffic mix & growth 

TM

Increasing # of 

connections & 

subscribers 

Increasing # of 

services & 

policies 

Higher bandwidth 

Higher Processing 

Requirements For 

Control & Data Plane 




Increasing Complexity 

Diversity of 

network traffic 

Lower power 

and cost 

TM





• Summary 




Agenda 

TM

QorIQ P5 

NEW: P5020, P5010 NEW! 

Up to 2.2GHz,

PLATFORMS 

QorIQ P5 

Up to 2.0 GHz,

eOpenPIC 

PreBoot Loader 

Security Monitor 

Internal BootROM 

Power Mgmt 

SD/MMC 

SPI 

2x DUART 

4x I2C 

2x USB 2.0 PHY 

Clocks/Reset 

GPIO 

CCSR 

eLBC 

32b 

Rapid 

IO 

RMan 

Pattern 

Match 

Engine 

2.0 

QorIQ P3 Series P3041 Processor Block Diagram 

Power Architecture ® 

128 KB 

Backside 

e500mc Core 

L2 Cache 32 KB 32 KB 

D-Cache I-Cache 

Coherency Fabric 

1024 KB 

Frontside 

L3 Cache 

64-bit 

DDR3/3L 

Memory Controller 

Peripheral 

PAMU PAMU 

PAMU PAMU PAMU 

Access Mgmt Unit 

SEC 

4.0 

Queue 

Mgr. 

Buffer 

Mgr. 

Frame Manager 

Parse, Classify, 

Distribute 

10GE 

Buffer 

1GE 

1GE 

CoreNet 




1GE 

1GE 

1GE 

PCIe 

PCIe 

SRIO 

SRIO 

PCIe 

DMA 

x2 

PCIe 

18-Lane 5 GHz SerDes 

• Pin compatible to P4080, P4040, P5020 & P5010 processors 

• 45nm SOI process 

SATA 2.0 

SATA 2.0 

Real Time 

Debug 

Watchpoint 

Cross 

Trigger 

Perf CoreNet 

Monitor Trace 

Aurora 

Quad e500mc Power Architecture ® 

• 4 cores (up to 1.5 GHz) with 128KB 

backside L2 cache 

• 1MB Shared L3 Cache w/ECC 

Memory Controller 

• 32/64bit DDR3/3L w/ECC up to 1.3 

GHz 

Ethernet 

• 5 x 10/100/1000 Ethernet controllers 

• 1 x 10GE controllers 

High Speed Interconnect 

• 4 PCI Express ® PCIe) 2.0 controllers 

• 2 Serial RapidIO ® 1.3 + 2.1 

controllers 

• 2 SATA 2.0 

• 2 USB 2.0 w/PHY 

CoreNet Switch Fabric 

Trusted Architecture 

Data Path Acceleration Architecture 

• Security Engine (SEC) 

• Pattern Matching Engine (PME) 

• Enhanced RapidIO Messaging 

(Rman) 

TM





• Summary 




Agenda 

TM

QorIQ P3041 




CoreNet Switch Fabric 

►Highly concurrent, 100% HW cache 

coherent, multi-ported fabric 

• Overcomes limitations of bus-based 

topologies 

• Completely eliminates retries for busy 

conditions or cache coherency actions 

• Variable snoop response timing 

• Current owner always supplies data 

• Minimizes average latency in congested systems 

• Flexible point to point connectivity 

• Variable number of different types of devices: Cores, 

Front-side caches, I/O, Memory controllers 

• Supports multiple, parallel address paths 

� High address bandwidth: Key for large coherent 

multicore processors 

• High data bandwidth 

� Crossbar connectivity: reduced contention provides low 

latency 

� Variable width data path per device provides 

throughput and power optimization 

� Capable of sustaining multiple cache lines per cycle to 

the cores 

� Supports future expansion to coherent multifabric 

‘clusters’ on SoC’s or coherent multichip 

systems 

� Architected to support heterogeneous 

Power Architecture ® cores in a single SoC, 

and heterogeneous Power + StarCore 

architecture cores in a single SoC 

TM





Frame Manager 

► Frame Manager is 

responsible for moving 

packets into and out of the 

data path 

• 5 Ethernet MACs 

� 5 x GbE 

� 1 x 10GbE 

• Parse 

• “Coarse” classification 

• Packet distribution across 

queues for load spreading 

• Policing 

TM


Data Path Infrastructure: Queue and Buffer Manager 




► Queue Manager supports 

the logical passage of frames 

of data between blocks 

functioning in the data path 

► Buffer Manager manages 

pools of buffers for storing 

frame data 

• Managed on behalf of 

software 

• Used by hardware 

TM





Pattern Matching Engine 

► Up to 32K patterns 

• Up to 256 sets 

• Up to 16 subsets 

► Up to 128B matched length 

► 5 Gbps raw scanning 

throughput 

► Pattern descriptions stored in 

DRAM 

► Stateful rules which tie 

multiple pattern matches 

together and create “patterns 

of patterns” 

TM





Security Block Version 4 

►Public key cryptography 

►Random number 

generation 

►Cryptographic 

authentication 

• SHA-1, SHA-2, MD5 

►Encryption and decryption 

• DES, 3DES, ARC, AES, 

Kasumi, Snow, … 

►From ~2 Gbps to 4 Gbps 

depending on algorithm 

►Advance protocol support 

• IPsec, SSL/TLS, 

LinkSec/MacSec, … 

►Run time integrity 

checking 

TM

Next Generation RapidIO ® Messaging Unit 

►QorIQ P4080 processor and all prior devices use existing Serial RapidIO 

messaging unit 

• QorIQ P4080 includes some messaging performance enhancements 

►All future devices with Serial RapidIO will use new Serial RapidIO 

messaging unit 

• Existing R/W capability retained in existing link controller 

• Implemented as “eMSG” for DSP, “RMan” for QorIQ 

• Improves Type 11 messaging performance 

� Lower CPU overhead 

� Full descriptor-based queuing mechanism 

– Data Path Acceleration Architecture (DPAA) enabled for QorIQ 

– Updates descriptor with classification info/byte count 

� More queues 

• Adds support for Type 9 data streaming 

� Line rate with low CPU overhead 

� Enhanced QoS 

• Adds selected Rev 2.1 features 

� Add 5.0 Gbaud operation 

� 2x lane support 

� Extended Type 9 Traffic Management 




MSC8156, QorIQ P4080 

Control RMU 

Link 

Controller 

Messaging 

Unit 

DSP MSC8155+ P304x, P5020 

Control eMSG Control RMan 

Link 

Controller 

Enhanced 

Messaging 

Unit 

Link 

Controller 

DPAA 

Messaging 

Unit 

TM





RapidIO ® Message Manager 

►RapidIO Rev 1.3 compliant 

with 2.1 features 

► Dual controllers 

► 1.25/2.5/3.125/5GBaud operation 

• 1x,2x,4x operation 

► Extensive transaction Type support 

• Type 9 data streaming 

• Type 10 doorbells 

• Type 11 messaging 

• NWRITE/SWRITE 

• Port-write 

► Support for hundreds of 

ingress/egress queues 

► Robust QoS 

► Direct interworking between 

Ethernet and RapidIO in hardware 

• No runtime CPU intervention 

required 

TM

Transactions Supported 

Queues 

New RapidIO ® Messaging Unit Comparison 

P4080 P3041 

Type 10 Doorbells 

Type 11 Messaging 

1 Type 10 Doorbell 

2 Type 11 Messaging 

Queue Arbitration Round Robin 

Outbound 




Type 5 NWRITE Type 9 Data Streaming 

Type 6 SWRITE Type 10 Doorbells 

Type 8 Port-Write Type 11 Messaging 

Thousands of queues supporting Type 5,6,8-11 

Data Path Acceleration Architecture 

• 3+3+1 SP+WRR 

Segmentation Resources 2 Segmentation Units 4 Segmentation Units 

Multicast Support Type 11 256B PDU to 16 Destinations Type 11 256B PDU to 32 Destinations 

Transactions Supported 

Queues 

Classification 

Inbound 

Type 8 Port-Write 

Type 10 Doorbells 

Type 11 Messaging 

1 Type 8 Port-Write 

1 Type 10 Doorbell 

2 Type 11 Messaging 

2 Rules (Fixed) 

Type 11: [mbox] 

Type 8 Port-Write Type 10 Doorbells 

Type 9 Data Streaming Type 11 Messaging 

1 Type 8 Port-Write 

1000s Type 9-11 

64 Rules (Exact or Wildcards) 

or 

Map selected header fields to queue ID 

Simultaneous Reassembly 

Contexts 

2 Type 11 

Additional Features 

16 Type 9, 11 

Traffic Management N/A Type 9: End-to-end XON/XOFF Per-Queue Flow Control 

TM

Protection Against 

Freescale QorIQ Platform’s - Trust Architecture 

• Theft of Functionality - loss of control of the system’s functionality 

• Theft of Data - where a data protection policy exists, loss of data to an unauthorized party 

• Theft of Uniqueness - loss of product differentiation through reverse engineering, 

duplication, and unapproved inter-operability. 

Relying on 

• Secure Boot – start from Trusted code base or don’t start at all 

• Strong Partitioning of the System – isolation of cores from each other to provide 

redundancy and data corruption protection between critical functions 

• Threat detection – internal and external security event detection 

• Secure Debug 




TM


PME 

SEC 4.0 

Run time 

integrity 

checker 

Security 

Monitor 

External 

Tamper 

Detection 

Circuits 

Trusted Architecture on QorIQ P3041 Processor 




Secure Platform Boot: 

Configured to boot from on-chip ROM 

• CPU#0 begins to boot from on-chip 

ROM, all other CPUs held in reset 

• CPU executing from on-chip trusted 

boot code (provided by FSL) 

performs initial SoC configuration 

and health checks, verifies a 

signature over the Hypervisor 

micro-kernel, stored in the NV RAM 

of OEM’s choice 

Secure boot insures that the system 

begins executing trusted code. This 

trusted code can test the 

trustworthiness of other system code 

before allowing it to execute. 

Note: ‘Trusted’ = passes signature 

check. Don’t sign it if you don’t trust it! 

P3041 Expanded Trust Architecture 

• Battery backed key for secure boot 

TM





• Summary 




Agenda 

TM




Overview of Markets 

P3041 Processor Markets 

►Networking 

• Integrated Access Routers 

• Enterprise Switching 

►Access 

• Base Station Network Interface 

Cards 

• Base Station Network Channel 

Cards 

►Industrial 

• Single Board Computers (SBC) 

• Aerospace and defense 

TM

Front panel 

access 

Flash code 

upgrade 

Front panel 

GE 

USB 

2.5Gb/s 

SGMII, 

XAUI, PCIe 

24x GE 

QorIQ 

P3041 

GE 

Switch 

SATA 

PCIe 

PCIe 

PCIe 

Switch 




GE 

PCIe 

Peripherals 

Out-of-band 

control path 

Backplane 

Data path 

Integrated Access Router 

Use Case Example 

P3041 Processor Benefits 

► Hypervisor supports safe partitioning 

between control plane and 

applications/user sandbox. 

► SATA for low-cost and high capacity 

storage 

► Multiple options for connection to GE 

switch 

• PCI Express ® interconnects 

• SGMII or 2.5Gb/s SGMII 

• XAUI 

► USB for front panel code upgrades 

► Trusted boot for IP protection 

TM

GE 

Maintence 

QorIQ 

P3041 

SGMII, 

2.5Gb/s SGMII 

XAUI 

SRIO 

Switch 

Backhaul to Access 

Gateway 

DSP 

DSP 

DSP 

(8156) 




LTE Wireless Base Station 

Use Case Example 

RF Components 

to Cellular User 

Equipment 

P3041 Processor Benefits 

►High Performance 

Interconnect between 

controller & DSPs 

• Has Serial RapidIO ® Rev 1.3 + 

2.1 with Type 9 & Type 11 

(Rman) 

►L2 & L3 Processing on 

quad cores (support for 

AMP/SMP) 

• Ideal for LTE 3 sector 

applications 

►Encryption support for UE 

(Kasumi/Snow3G) and 

Backhaul (IPSec) 

►Power optimized for 12W 

channel cards 

TM

►Wide variation of customer use-cases 

• Multiple operating systems utilized across cores on a single device 

• Proprietary, 3 rd party and Open Source multicore operating systems 




Multicore Operating Systems 

• Symmetric Multi-Processing (SMP) and Asymmetric Multi-Processing (AMP), often running concurrently 

• Often no OS, or engineered light OS, used on forwarding/data plane cores 

►Leverage Power Architecture ® technology’s 3 rd party OS ecosystem 

• Enabled by 

� Freescale embedded hypervisor 

� Freescale boot standards, including u-boot 

� Leverage open boot protocol and API standards (e.g. Power.org) 

� Freescale Light Weight Executive (LWE) for run to completion data plane processing 

� Demonstrate performance and provide reference example for customers 

Services 

Linux ® 

L2 Cache 

Power Architecture® 

Core 


Forwarding/ Data Plane Control Plane 

L2 Cache 

Power Architecture 

Core 


Light Weight 

Executive 

AMP 

L2 Cache 

(Light 

RTOS) 


Core 


3 rd Party 

L2 Cache 


Core 


TM




P3041 Processor Announced Ecosystem 

Strategic Alliance Partners 

Ecosystem Partners 

Freescale Foundation Enablement 

CodeWarrior 

VortiQa 

TM



• New QorIQ P3041 Accelerators Overview 


• Summary 




Agenda 

TM

Feature Benefit 

Four high-performance 

cores 

► Supports flexible allocation of resources to control and data plane, with 

Hypervisor enabling robust AMP implementation 

► 1.5 GHz cores enable high performance control plane 

Value Performance ► Double the performance of MPC8572 at similar price 

High performance 

acceleration 

Pin compatibility with 

P4 platform 

► 5Gb/s IP Forwarding with 64B packets 

► DPAA offloads CPU for upper layer functions 

► Pin compatibility with same programming model of P4080 allows a single board 

to offer multiple performance levels. 

► Allows drop-in significant cost reduction for customers using P4040 

Low power ► Fits 12W – 15W thermal max budgets of NIC cards and other applications in 

challenging environments 

► Power reduction for MPC8572 sockets. 

Serial RapidIO ® 

Improvements 

► Supporting up to 5 GHz for high control and data throughput 

► RapidIO Message Manager (RMan) allows packets (Type 9 and 11) to plug 

directly into DPAA for greater CPU offload 

Dual SATA Board-cost savings by integrating high-capacity disk storage interface 

Flexible SerDes 

configuration 




QorIQ P3 Features/Benefits 

Per bank SerDes selection enables optimal per-application SerDes allocation 

TM

Introducing QorIQ P3041 Processor - Freescale

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