Digital to Analog Converter - AN0022 - Application ... - Energy Micro

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3 Advanced Features...the world's most energy friendly microcontrollers3.1 Sine Generator ModeThe DAC contains an automatic sine generator mode, which is enabled by setting the SINEMODE bitin the DACn_CTRL register. In this mode, the DAC data registers are overridden with conversion datataken from a hardware sine lookup table. The lookup table consist of 16 samples. When the OUTENPRSbit in DACn_CTRL is cleared, the sine generator will output the next sine-sample when a PRS conversiontrigger pulse is received. This is illustrated in Figure 3.1 (p. 6) .Figure 3.1. Sine Generator Mode with PRS-triggered SamplesOne PRS HFCLK PulsePRS pulse period changedCH0 PRSDACn_OUT0Sine Sam plesBy having a timer supply the PRS pulses on compare or overflow the frequency of the sine wave canbe accurately controlled.If the OUTENPRS bit is set, the PRS channels selected by PRSSEL in DACn_CH0CTRL andDACn_CH1CTRL switches on and off the sine wave (CH0 PRSSEL) and output driver (CH1 PRSSEL).The sine generator will now trigger new conversions by itself. If the channel 0 PRS line is low, a voltageof Vref/2 will be produced. When the line is high, the sine wave will be produced. The PRS line selectedfor channel 1 controls the output-driver which is tristated when the PRS line is low. This is illustratedin Figure 3.2 (p. 7) .The frequency when the OUTENPRS bit is set is given by Equation 3.1 (p. 6) :Sine Generation with OUTENPRS bit setf sine = f HFPERCLK / 32 x (PRESC + 1) (3.1)The sine wave will be output on channel 0. If the DIFF bit is set in DACn_CTRL, the sine wave will beoutput on both channels (if enabled), but inverted on the second channel (see Figure 3.2 (p. 7) ).Note that when OUTENPRS in DACn_CTRL is set, the sine output will be reset to 0 degrees when thePRS line selected by CH0PRSSEL is low.2013-05-08 - an0022_Rev1.09 6 www.energymicro.com
Figure 3.2. Sine Generation with OUTENPRS bit setCH0 PRS...the world's most energy friendly microcontrollersCH1 PRSVrefDACn_OUT1Hi-ZVref/20VrefDACn_OUT0Hi-ZVref/20In Figure 3.2 (p. 7) , when the OUTENPRS bit in DACn_CH0CTRL is set, the PRS-lines selectedby CH0PRSSEL and CH1PRSSEL enables the output driver and starts or stops the sine generator.3.2 Peripheral Reflex System and InterruptsBoth DAC channels have separate interrupt flags (in DACn_IF) indicating that a conversion has finishedon the channel and that new data can be written to the data registers. Setting one of these flags will resultin a DAC interrupt request if the corresponding interrupt enable bit is set in DACn_IEN. All generatedinterrupt requests from the DAC will activate the same interrupt vector when enabled.The DAC has two PRS outputs which will carry a one cycle (HFPERCLK) high pulse when thecorresponding channel has finished a conversion.3.3 Direct Memory AccessIn addition to the PRS output, the DAC sends out a DMA request when a conversion on a channel iscomplete. This request is cleared when the corresponding channel´s data register or the COMBDATAregister is written.3.4 CalibrationThe DAC contains a calibration register, DACn_CAL, where calibration values for both offset and gaincorrection can be written. Offset calibration is done separately for each channel through the CHxOFFSETbitfields. Gain is calibrated in one common register field, GAIN.The calibration values are linked to the reference and when the reference is changed, the correctcalibration values should be written to the calibration register. Gain and offset for the 1V25, 2V5 andVDD references are calibrated during production and the calibration values for these can be found inthe Device Information page. The correct calibration values are loaded automatically when using theemlib for configuring the DAC.The DAC can also be calibrated manually. Either the internal ADC or an external voltage meter can beused to measure the DAC output voltage. If the ADC is used, it should be calibrated first as describedin the AN0021 - ADC application note. The procedure for calibrating the DAC is similar to the ADCcalibration procedure.• Offset is calibrated first by converting the value 0, and changing the calibration register until the outputequals 0 V. The algorithm should take into account that the offset might be far below 0, but the outputwill still be 0.2013-05-08 - an0022_Rev1.09 7 www.energymicro.com
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Page 3 and 4: 2 General Operation2.1 Clock Presca
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Page 15 and 16: A Disclaimer and TrademarksA.1 Disc
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Digital to Analog Converter - AN0022 - Application ... - Energy Micro

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