Using the Enhanced Local Bus Controller "eLBC" in ... - Freescale

June, 2010 

Using the Enhanced Local Bus Controller "eLBC" 

in PowerQUICC and/or QorIQ Processors 

FTF-NET-F0809 

Zhongcai Zhou 

Application Engineer 

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., 

Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink 

and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 

TM

Agenda 

►eLBC Overview 

►General Purpose Chipselect 

Machine (GPCM) 

►NAND Flash Control 

Machine (FCM) 

►User Programmable 

Machine (UPM) 




2 

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How to Use the Enhanced Local Bus Controller (eLBC) 

in PQ and/or QorIQ 

►After the power is turned on, a typical system: 

1. Starts execution from non-volatile memory, typically flash memory 

2. Copies/loads the code to main memory (DDRx) 

3. Starts the execution from the main memory 

Core 




2 

1 

3 

U-boot/ 

BIOS 

Flash 

Storage 

ROMzz/Hard Drive 

Main Memory 

DDRx 

3 

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System Must Talk to Flash Memory Without Any Configuration 

►A system must be able to talk to non-volatile memory without any 

configuration steps 

►eLBC is the controller that does this initial booting job 

• eLBC has three controllers: 

1. General purpose chip-select machine (GPCM) 

– Regular NOR flash for booting 

– SRAM or FPGA 

2. NAND flash control machine (FCM) 

– NAND memory for storage and/or booting 

3. User programmable machine (UPM) 

– FPGA, ZBT RAM, etc. 




4 

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5 

eLBC Diagram 

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Basic Operation 

► A transaction request comes to the local bus with address/size/ 

read-write 

► The address is compared against the BRx and ORx to determine which bank(#CS) 

this address belongs to 

• There is one BR/OR pair for each bank(#CS) 

► The transaction is routed to the corresponding controlled determined by BR[MSEL] 

BRx 

ORx 

BA: Base Address 

PS: Port Size 

V : Valid 

AM: Address Mask 

MSEL: Machine Select 

AM Controller dependent 

000 GPCM 101: UPMB 

001 FCM 110: UPMC 

100: UPMA others: Reserved 

6 

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Boot from eLBC 

► Flexibility of programming each CS to any one of the controllers (GPCM, FCM, 

UPMA, UPMB, UPMC) 

► CS0 is special 

If the device is configured to boot from the local bus, then the boot ROM, either 

flash or NAND, must be connected to /CS0 

BR0 and OR0 will be set by the hardware automatically to appropriate value: 

Boot from GPCM 

8-bit ROM 

Boot from GPCM 

16-bit ROM 

Boot from NAND 

8-bit small page 


8-bit large page 

Boot from 

non-eLBC interface 

BR0[PS] BR0[MSEL] BR0[V] FCM: OR0[PGS] 

8-bit(01) GPCM(000) 1 x 

16-bit(10) GPCM(000) 1 x 

8-bit(01) FCM(001) 1 Small page(0) 

8-bit(01) FCM(001) 1 Large page(1) 

x x 0 x 

7 

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Boot from eLBC (cont.) 

►OR[AM] set to all 0 

This means all the address bits are masked and not used for the 

comparison. Any address hits bank 0. The bank size is 4 GB. 

►How about timing? 

GPCM or FCM is set most conservatively in terms of timing out 

of reset. This guarantees that GPCM or FCM can talk to any flash or 

NAND. 

►The boot code should shrink the bank size and adjust the timing according 

to the specific boot memory used to speed up the booting process. 

8 

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►Address and data are big-endian indexed 

LAD[0:31]: LAD[0] is the MSB; LAD[31] is the LSB 

LA[16:31]: LA[16] is the MSB, LA[31] is the LSB 




Key Feature of eLBC 

►Buffer control 

LBCTL: The LBCTL pin functions as a write/read control for a bus transceiver 

connected to the LAD lines 

►Register writing and local bus request are two different ports. The race 

condition is possible. 

For example, in the code: 

write(eLBC register) 

read from eLBC 

eLBC could start the read before write32 takes effect. Change to: 

write(eLBC register) 

read(same eLBC register) 

read from eLBC 

9 

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Key Feature of eLBC: It Is a Multiplexed Bus 

► Address and data are multiplexed in the same pins to reduce pin counts. 

► LALE (Local bus Address Latch Enable): Indicates the address phase 

• There are two main variations: 

32-bit bus: 

LAD[0:31] 

LA[25:31] 

lad[0:26] la[0:26] 

lale 

latch 

la[25:31] 

la[0:31] 

Advantage: Higher performance 

16-bit bus: 

LAD[0:15] 

LA[16:31] 

lad[0:15] la[0:15] 

lale 

latch 

la[16:31] 

10 

la[0:31] 

Advantage: Fewer pins, narrower latch 

TM

► Port size and address connection 

• This applies to GPCM and UPM 

• 1 MB Flash 

LA[12] 

LA[30] 

LA[31] 

LAD[0:7] 

8-bit port 

A18 

A0 

LA[12] 

LA[29] 




Key Feature of eLBC (cont.) 

A-1 LA[30] 

A0 LA[29] 

A0 

LAD[0:15] 

16-bit port 

A18 

A1 

LA[12] 

LA[28] 

LAD[0:31] 

32-bit port 

A17 

A1 

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►Debug feature 

• When an error happens, the transaction info is logged into: 

� LTEAR ( Transfer Error Address Register) 

� LTEATR (Transfer Error Attributes Register) 

►Bus monitor 




Key FEATURE of eLBC 

12 

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►The simplest among the three controllers 

►Designed to interface to flash devices 

General Purpose Chip-select Machine (GPCM) 

►Typical flash signals and timing (from a flash device datasheet) 

Generic Flash Read Timing Generic Flash Write/Program Timing 




13 

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GPCM Timing Control 

► GPCM needs to control the relative timing between the address, /CS, /WE, /OE 

signals 

► All the timings are controlled by OR register 

CSNT: /LCS and LWE negation timing 

ACS: Address to /CS setup time 

XACS: Extra address to /CS setup time 

TRLX: Timing relaxed 

EHTR: Extended hold time on read access 

EAD: LALE width control 

14 

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There is a table in the manual listing the 

timings for all the parameter combinations. 

► t ARCS 

• Mainly controlled with OR[ACS] 

• Recommended to set to ACS=00 

tAwCS=0 • This gives one cycle address to /CS setup 

time (address starts with LALE assertion). 

Sufficient for flash 

► t AOE 

• At least one cycle. Sufficient for flash 

• No programming needed 

► t RC/ t CSRP 

• Mainly determined by OR[SCY] 

• Programmed according to flash speed 

► t OEN 

• Controlled with OR[CSNT] 

• There is one automatic cycle between a read 

and next transaction 

• Program to 0 for most flashes 

• Only flash that shuts off very slowly after read 

needs to add extended cycles 




How to Program GPCM Read Timing 

15 

Read Timing 

TM

There is a table in the manual listing the 

timings for all the parameter combinations. 

► t AWCS 

• Mainly controlled with OR[ACS] 

• Recommended to set to ACS=00 

tAwCS=0 • This gives one cycle address to /CS setup 

time (address starts with LALE assertion). 

Sufficient for flash 

► t AWE 

• At least one cycle. Sufficient for flash 

• No programming needed 

► t WC/tCSWP 

• Mainly determined by OR[SCY] 

• Programmed according to flash speed 

► t WEN 

• Controlled with OR[CSNT] 

• Program to 0 for most flashes 




How to Program GPCM Write Timing 

16 

Write Timing 

TM




Connection Example: Both NAND and NOR 

17 

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►External GTA termination 




Key Feature of GPCM 

• GPCM is terminated by programmed cycle number or LGPL4/GTA if 

asserted earlier. 

• OR[SETA] =‘1’: GPCM ignores OR[SCY] and terminated by GTA only. 

• This feature is useful for some devices that have variable access time. 

►Why do we need LA[27:31]? 

►No support for burst 

• What happens if a burst request goes to GPCM? 

18 

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►Overview of NAND flash 

• Higher density than regular flash (NOR flash) 

• IO device using commands to read/write 

� No address bus 

� Page-oriented, not suitable for random access 

� No execute in place 

• Possible bit error 




NAND Flash 

� Usually a certain number of blocks are marked bad by the manufacturer 

� During the operation, more blocks can go bad 

� ECC is a must 

19 

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CE: Chip Enable 

WE: Write Enable 

CLE: Command Latch Enable RE: Read Enable 

ALE: Address Latch Enable 

Observation: There is no address bus 

Note: Data bus must be bit reversed. 




NAND FCM Connection 

20 

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cmd1 cmd2 




21 

How to Read NAND 

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22 

How to Write NAND 

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►Different vendors might have slightly different sequences. 

►The commands might be different. 




Observations 

►In order to talk to all the vendors, FCM takes a generic approach. 

User has the flexibility/responsibility to define the command 

sequence. 

►512K vs. 2K 

23 

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How FCM Operates 

►Internal 8K buffer. Data is exchanged through buffer normally. User 

has the option to read/write single byte from MDR register. 

core 

• For large page size NAND, 8K is split into two 4K-buffers. 

4K-buffer: 2K for main region, 64 bytes for spare. 

4K 

4K 

• While one 4K buffer is exchanging data with NAND, the core can access 

the other 4K-buffer. 

• For small page sizes, there are 8 1K-buffers. 

24 

NAND 

TM

►Write data 

1. Initialize FCM registers for write 

2. Set FMR[OP]=00, normal operation 

Write to the buffer 

3. Set FMR[OP]=11 after the data (usually one whole page) 

is in the buffer 

4. Dummy write to memory bank 

or write to LSOR to start the write sequence 

5. FCM reads data from buffer, writes to NAND 




25 


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►Read data 

1. Initialize FCM registers for read 

2. Set FMR[OP]=11 

3. Dummy write to memory bank 

or write to LSOR to start the read sequence 

4. When the data read is finished, the status bit is set 

5. Set FMR[OP]=00, normal operation 

read data from the buffer 




26 


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►Command sequence control 

►Timing control 




27 

Programming Model 

TM

►Flash instruction register (FIR) 

FCM starts with OP0, until it encounters OPx=0000 

User must program the sequence according to the NAND datasheet. 

OP definition 

0000: NOP. End of sequence 1000: WB. Write FBCR bytes 

0001: CA. Column Address 1001: WS. Write one byte 

0010: PA. Block+Page address 1010: RB. Read FBCR bytes 

0011: User-defined address 1011: RS. Read one byte 

0100: CM0. Cmd from FCR[CMD0] 1100: CW0. Wait R/B. Issue FCR[CMD0] 

0101: CM1. Cmd from FCR[CMD1] 1101: CW1. Wait R/B. Issue FCR[CMD1] 

0110: CM2. Cmd from FCR[CMD2] 1110: RBW. Wait R/B. Read FBCR bytes 

0111: CM3. Cmd from FCR[CMD3] 1110: RSW. Wait R/B. Read one bytes 




Command Sequence Control 

28 

TM

►Read sequence programming (slide 19) 

FIR 




Command Sequence Control Example 

OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 

CM0 CA PA CM1 RBW NOP 

0100 0001 0010 0101 1110 0000 

FCR CMD0 CMD1 CMD2 CMD3 

0x00 0x30 

For CA (column address), the controller handles the length 

automatically according to ORx[PGS], the page size field. 

It is one cycle for small-page NAND and two cycles for large-page NAND. 

For PA (page address) 

The controller handles the length based on FMR[AL]. 

29 

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►Write sequence programming (Slide 20) 

FIR 




Command Sequence Control Example 

OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 

CM1 CA PA WB CM2 CW0 RS NOP 

0101 0001 0010 1000 0110 1100 1011 0000 

FCR CMD0 CMD1 CMD2 CMD3 

0x70 0x80 0x10 

30 

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Timing Control: Command/Address/Data Write 

►The timing is controlled by OR[CST], OR[CHT], OR[TRLX]. 

• There is a table in the manual listing all the combinations. 




31 

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►The timing is controlled by OR[RST], OR[TRLX]. 




Timing Control: Data Read 

• There is a table in the manual listing all the combinations. 

32 

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►When eLBC is configured to boot from NAND 

• FCM automatically reads 4K data from NAND to the buffer 





• Core waits until this 4K transfer finishes, then executes the code out of 

this 4K buffer 

• This 4K code cannot call the function outside of the 4K range. It needs 

to copy the rest of the code to DDR and continue the bootstrap process 

33 

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►Very flexible timing 

►Supports burst 

• Better performance than GPCM 

►There are three independent UPMs. 

User Programmable Machine (UPM) Controller 




34 

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Basic Principle of Operation 

UPM Routine Start Address 

Read single-beat 0x00 

Read burst 0x08 

Write single-beat 0x18 

Write burst 0x20 

Refresh Timer 0x30 

Exception Condition 0x3C 

35 

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Programming Model 

►UPM reads the appropriate RAM array based on the transaction 

type: read/write, single/burst 

►RAM array instructs the controller what level to drive to each signal 

36 

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►Basic Timing 

• CST1-4: LCS level at phase 1-4 

• BST1-4: LBS level at phase 1-4 




Programming Model: RAM Array 

These two signals can be controlled to a resolution of a quarter of LCLK. 

• G0L/H: LGPL0 level control 

• G1-5T1: LGPL1-5 level at phase 1 and 2 

• G1-5T3: LGPL1-5 level at phase 3 and 4 

These signals have resolution of half clock 

37 

TM

I 

N 

D 

E 

X 

C 

S 

T 

1 

C 

S 

T 

2 

C 

S 

T 

3 

C 

S 

T 

4 

B 

S 

T 

1 

B 

S 

T 

2 




B 

S 

T 

3 

B 

S 

T 

4 

G 

0 

L 

G 

0 

H 

0 1 0 1 1 1 1 0 0 10 11 0 1 0 1 0 1 0 1 0 1 

1 1 1 0 0 0 0 1 1 11 10 0 0 1 0 1 0 1 0 1 0 

LCLK 

LCS 

LBS 

LGPL0 

LGPL1 

T1 T2 T3 T4 T1 T2 T3 T4 

G 

1 

T 

1 

G 

1 

T 

3 

G 

2 

T 

1 

G 

2 

T 

3 

38 

Basic Timing Control 

G 

3 

T 

1 

G 

3 

T 

3 

G 

4 

T 

1 

G 

4 

T 

3 

G 

5 

T 

1 

G 

5 

T 

3 

TM

Advanced features: 

► There are only 8-entries for single read/write, 16-entries for burst read/write. 

• If this is insufficient, then 

REDO: Redo current RAM array once, twice, three times 

LOOP: 

RAMx LOOP=1, loop start 

……………… 

RAMy LOOP=1, loop end 

Loop Number: MxMR[RLF] for read and MxMR[WLF] for write 

• If this is insufficient, then 

REDO: 

LOOP: 

RAMx LOOP=1, loop start 

……………… 

RAMy LOOP=1, loop end 

Loop Number: MxMR[RLF] for read and MxMR[WLF] for write 

NA: Next address. Increment LA[27:31]/ 

UTA: UPM TA assertion 

LAST: Last entry 

► Less common/useful fields: 

• EXEN: Exception enable 

• AMX: Address muxing 

• TODT: Turn-on disable timer 




39 

RAM Array (cont.) 

TM

►LGPL4/UPWAIT 

• UPM supports wait signal to handle variable-speed devices 

• LGPL4/UPWAIT can be programmed as either 

� LGPL4, an output 

� UPWAIT, an input 

►Polarity of UPWAIT is programmable (MxMR[UWPL) 




40 

UPWAIT 

TM

Using the Enhanced Local Bus Controller "eLBC" in ... - Freescale

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