eFlexPWM - Freescale Semiconductor

June, 2010 

Getting Started with Digital Signal Controllers (DSCs) 

for Motor Control and Energy Conversion 

FTF-IND-F0580 

Pavel Grasblum, Ph.D. 

Application Engineer 

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale 

Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC 

Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 

Freescale Semiconductor, Inc. 

TM

►DSC Introduction 

• Roadmap Update 

• DSCs Overview 

►DSC Core Introduction 

►Key peripherals for Motor Control and Energy Conversion Applications 

• Detail Description 

• Differences among DSC Families 

►Peripherals Utilization Guidelines 

• ADC to PWM Synchronization 

• Low Cost Current Measurement 

• BLDC Motor Commutation 

►MC and SMPS Demos presented at FTF in Orlando 





2 

Agenda 

TM

• Designed for controller code 

• Compact code size 

• Easy to program 

• Inefficient signal processing 





What is a Digital Signal Controller? 

► Instructions optimized for controller code, DSP, matrix operations 

► Compact assembly and “C” compiled code size 

► Easy to program 

► Additional MIPS headroom and extended addressing space 

3 

• Designed for DSP processing 

• Designed for matrix operations 

• Complex programming 

• Less suitable for control 

TM

When is a Digital Signal Controller a Good Fit? 

► When the application is dominated by high-speed capture and analysis of analog 

input and feedback (e.g. PWM adjustment) to a closed loop system 

• DSC is similar to an MCU but with the performance to run complex algorithms for more 

responsive control and often, system cost reduction 

• DSC provides flexibility to be used in multiple systems or to adapt within a system to 

environmental changes (compared to fixed analog-based control) 

► Key features 

• Sufficient MIPs (32-60 MIPS) MCU/DSP performance for advanced algorithms 

• High speed/performance 600ns/12 bit ADC for fast dynamic response 

• High speed sophisticated (60 MHz- 96 Mhz) PWMs and timer modules to effectively 

increase PWM resolution 

• Quadrature decoders for direct interface to Hall effect sensors or optical encoders 

• Safety features (fault inputs, loss of clock…) to prevent catastrophic failures 

► Key applications 

• Motor control 

• Digital power conversion 

• Advanced lighting control 





4 

TM

Flash 

Size 

► 32 MIPS performance 

► 12K -16 K Bytes program FLASH 

► 4 K Bytes program/data RAM 

► Tunable internal relaxation oscillator 

► Software programmable phase locked loop 

► Up to 96 MHz peripherals – timers and PWMs 

► Up to 6-output PWM module with up to 4 

programmable fault inputs 

► Two 12-bit ADCs with up to 8 inputs, 1.125us 

conversion rate 

► Synchronization between PWM and ADC 

► Four 16-bit general purpose programmable timers 

► Computer operating properly timer 

► Serial ports: SCI, SPI, I 2 C 

► Up to 26 GPIOs – Versatile pin usage 

► Low power consumption – 59 mA max. and 

.026 mA min. 

► JTAG/EOnCE debug port 

► Industrial and automotive temperature range 

► Cost effective 





Cost-Effective 56F8000 Solutions (56F801x) 

12K - 16KB 

Program Flash 

4kB 

Program/ 

Data RAM 

56800E Core 

32MHz 

JTAG/EOnCE 

56F8011/56F8013/56F8014 

System Integration Up to 26 GPIOs 

Module (SIM) 1 x SCI 

Interrupt Controller 1 x SPI 

PLL 

1x IIC 

Relaxation OSC 3-4ch 12bit ADC 

3-4ch 12bit ADC 

Voltage Regulator 

Synch 

COP 

4Ch 16bit Timer 

Power-On-Reset 

Power Supervisor 

6 

6-ch PWM Output 

Package: 32LQFP 

In Production 

TM

► 32 MHz/32 MIPS 56800E core 

► 3.0-3.6V operation 

► 32K-64 K Bytes program FLASH 

► 4K-8 K Bytes program/data RAM 

► Flash security 

► Tunable internal relaxation oscillator 



► 6 output PWM module with 4 programmable fault 

inputs with selectable PWM frequency for each PWM 

signal complementary pair 

► Two 12-bit ADCs with up to 16 inputs , 1.125us 

conversion rate 

► Up to two 12-bit digital to analog converters 

► Two analog comparators 

► Synchronization between PWM and ADC 

► 4 or 8 16-bit general purpose programmable timers 

► 1 or 3 programmable interval timers (PIT) 


► 2-queued serial communications interface 

► 2-queued serial peripheral interface 

► Optional MSCAN 

► I 2 C communications interface 

► Up to 53 GPIOs – Versatile pin usage 


► Industrial and automotive temperature range 

56F8000 Family Expansion (56F802x/56F803x) 

32KB - 64KB 

Program Flash 

4kB-8KB 

Program/ 

Data RAM 

56800E Core 

32MHz 

JTAG/EOnCE 





56F8023/56F8025/56F8036/56F8037 


Module (SIM) 2 x QSCI 

Interrupt Controller 2 x QSPI 

PLL 

1xIIC 

1x MSCAN 

Relaxation OSC 

3xPIT 

Crystal OSC 8ch 12bit ADC 

8ch 12bit ADC 


COP 


Synch 

8Ch 16bit Timer 


2 x 12 bit DAC 

Package 32 LQFP, 44LQFP, 48LQFP, 64LQFP 

In Production 

7 


2 x Comparators 

TM

► 32 MHz/32 MIPS 56800E core 


► 12K - 16K Bytes program FLASH with Flash security 

► 2K Bytes program/data RAM 

► Tunable internal relaxation oscillator and 32 KHz clock 

► Phase locked loop (PLL) 

► Up to 96 MHz peripherals – timers, PWM & Hi-SCI 

► 6 output PWM module with 4 programmable fault inputs 

with selectable PWM frequency for each PWM signal 

complementary pair 

► Two programmable gain amplifiers with x2, x4, x8, x16 

gains (clocked in order to cancel input offset) 

► Two 12-bit ADCs with up to 24 inputs , 2.5us per 

conversion 

► Programmable delay block provides precise control of 

ADC/PGA sample times relative to PWM reload cycles 

► Three high speed analog comparators 

► 2 multiple function programmable timers 


► One periodic interval timer (PIT) 

► 1 high speed serial communication interface (Hi-SCI) 

► 1 serial peripheral interface (SPI) 

► I 2 C communications interface 

► Up to 40 GPIOs – versatile pin usage 


► Industrial temperature range: -40C – 105C 

12-16KB 

Program 

Flash 

2KB 

Program/ 

Data RAM 

56800E 

Core 

32MHz 

JTAG/EOnCE 





Ultra Low Cost: 56F800x 

56F8002, 56F8006 


Module (SIM) 1 SCI 

Interrupt Controller 1 SPI 

PLL 

1 IIC 

2 x 16bit Timers 


Crystal OSC 

1 Period Int Timer 




8 

COP 

3 x Analog 

Comparators 

2 x Programmable 

Gain Amplifiers 

12ch 12bit ADC 

12ch 12bit ADC 

Synch 

Programmable 

Delay Block 


Package: 28SOIC, 32SDIP , 32LQFP, 48 LQFP 

In Production 

TM





56F8000 Series Feature Summary 

56F8002 56F8006 56F8011 56F8013 56F8014 56F8023 56F8025 56F8036 56F8027/37 

Performance 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 

Temperature Range (V) -40C~105C -40C~105C -40C~125C -40C~125C -40C~125C -40C~105C -40C~105C -40C~105C -40C~105C 

Voltage Range 1.8V - 3.6V 1.8V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 

Voltage Regulator On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip 

Program/Data Flash 12KB 16KB 12KB 16KB 16KB 32KB 32KB 64KB 32KB / 64KB 

Program/Data RAM 2KB 2KB 2KB 4KB 4KB 4KB 4KB 8KB 4KB /8KB 

Program Security Yes Yes Yes Yes Yes Yes Yes Yes Yes 

On Chip Relaxation Osc. Yes Yes Yes Yes Yes Yes Yes Yes Yes 

PLL Yes Yes Yes Yes Yes Yes Yes Yes Yes 

COP (Watchdog) Yes Yes Yes Yes Yes Yes Yes Yes Yes 

PWM (96 Mhz Clock) 1 x 6ch 1 x 6ch 1 x 6ch 1 x 6ch 1 x 5ch 1 x 6ch 1 x 6ch 1 x 6ch 1 x 6ch 

PWM Fault Inputs 4 4 4 4 3 4 4 4 4 

12-bit ADCs 2 x 8ch 2 x 12ch 2 x 3ch 2 x 3ch 2 x 4ch 2 x 3ch 2 x 4ch 2 x 5ch 2 x 8ch 

12-bit DACs 0 0 No No No 2 2 2 2 (Pinned out) 

Analog Comparator 3 3 No No No 2 2 2 2 

Prog Gain Amp 2 2 No No No No No No No 

16-bit Timers 3 3 4 4 4 4 4 4 8 

Prog. Interval Timers 1 (RTC) 1 (RTC) No No No 1 3 3 3 

GPIO (max) (+/-8mA) 23 40 26* 26* 26* 26* 35* 39* 53* 

IIC 1 1 1 1 1 1 - QIIC 1 - QIIC 1 - QIIC 1 - QIIC 

SCI (UART) / LIN Slave 1 - SCI 1 - SCI 1 - SCI 1 - SCI 1 - SCI 1 - QSCI 1 - QSCI 1 - QSCI 1 - QSCI 

SPI (Synchronous) 1 - SPI 1 - SPI 1 - SPI 1 - SPI 1 - SPI 1 - QSPI 1 - QSPI 1 - QSPI 1 - QSPI 

CAN No No No No No No No MSCAN MSCAN 

JTAG/EOnCE Yes Yes Yes Yes Yes Yes Yes Yes Yes 

Power Consumption IDD = 45.6mA;IDDA = 4.5mA IDD = 42mA; IDDA = 13.5mA IDD = 48mA; IDDA = 18.8mA IDD = 48mA; IDDA = 18.8mA 

Package 32LQFP 28SOIC 32LQFP 32LQFP 32LQFP 32LQFP 44LQFP 48LQFP 64LQFP 

(.8p) 32LQFP 

32SDIP 

48LQFP 

TM

Flash 

Size 

► 60 MHz/60 MIPS from 56800E core 


► 64K Bytes program FLASH 

► 8K Bytes program/data RAM 

► Flash security 

► 8Mhz/100Khz tunable internal relaxation oscillator 



• 8 output PWM module 

• 520ps PWM and PFM resolution 

► 2-12-bit ADCs with total 16 inputs 

• 600ns conversion rate 

• built-in PGA with 1x, 2x, 4x, gains 

► 1 12-bit digital to analog converter 

► 3 5-bit digital to analog converters 

► 3 analog comparators 

► 8 16-bit enhanced GP multifunction 

programmable timers 

► Cyclic redundancy check generator (CRC) 


► 2 high speed serial communications interface (SCI) 

► 1 queued serial peripheral interface (QSPI) 

► 1 MS-CAN bus 

► 2 I 2 C/SMbus communications interface 

► Up to 54 GPIOs 

► Inter module cross-bar 


► Industrial temperature range: -40°C to 105°C with 

60 Mhz 





MC56F824x/MC56F825x Features 

64KB 

Program Flash 

8kB 

Data RAM 

56800E Core 

60 Mhz 

JTAG/EOnCE 

System Integration 

Module (SIM) 

Interrupt Controller 

8ch 12-bit ADCA 

Crystal Oscillator 

44LQFP, 48LQFP 64 LQFP, Samples Available 

11 

PLL 


COP 

POR 

LVI 

Prog Gain Amp Ax1,2,4 

8ch 12-bit ADCB Prog Gain Amp Bx1,2,4 

CRC 


8-ch High Res PWM 

1ch 12-bit DAC 

3 5-bit DAC 

3 Analog Comparators 

2 x High Speed QSCIs 

1 x QSPI 

2x IIC/SMbus 

1 x MSCAN 

8Ch 16-bit Timer 

Inter-module Cross Bar 

►Breakthrough Features: 

• New generation high speed PWM module 

� 520 ps duty cycle and frequency resolution 

� Flexible edge placement 

• High speed ADC with programmable gain amplifiers 

� 600ns conversion rate 

� Supports multi trigger source in one ADC scan 

• Inter-module cross bar 

� Programmable inter module connection 

TM

► Instruction Fetch: 

PAB - 21 bits 

PDB - 16 bits 

► 1st Data Access: 

XAB1 - 24 bits 

CDBR - 32 bits 

CDBW - 32 bits 

► 2nd Data Access: 


XDB2 - 16 bits 

► Operations Performed: 

1st - PAB / PDB 

2nd - XAB1 / 

DBR- 

CDBW 

3rd - XAB2 / 

XDB2 

PC 

LA 

LA2 

HWS 

FIRA 

FISR 

SR 

OMR 

LC 

LC2 

PROGRAM 

CONTROLLER 

BIT 

MANIPULATION 

UNIT 

EOnCE/JTAG 

TAP 

INSTRUCTION 

DECODER 

INTERRUPT 

UNIT 

LOOPING 

UNIT 





A2 

B2 

C2 

D2 

A1 

B1 

C1 

D1 

Y0 

Y1 

X0 

MAC 

and ALU 

DSP56800E Core Architecture 

AGU ALU1 ALU2 

M 01 

N 3 

A0 

B0 

C0 

D0 

R0 

R1 

R2 

R3 

R4 

R5 

N 

SP 

Multi-bit 

Shifter 

DATA 

ALU 

12 

XAB1 

XAB2 

PAB 

PDB 

CDBW 

CDBR 

XDB2 

Program 

Memory 

Data 

Memory 

IP-Bus 

Interface 

External 

Bus 

Interface 

TM

N −1 





Mapping the Architecture to DSP Algorithms 

yn ()= ∑ ci () xn−i i = 0 

OPCODE AND OPERANDS 

( ) ; Typical Digital Filter Formula 

Source 1 Destination 1 

Parallel Move 

PRIMARY READ 

(Uses XAB1 and CGDB) 

Source 2 Destination 2 

MACR X0,Y0,A X:(R0)+N,Y0 X:(R3)-,X0 

SECONDARY READ 

(Uses XAB2 and XDB2) 

13 

TM

PC 

LA 

LA2 

HWS 

FIRA 

FISR 

SR 

OMR 

LC 

LC2 

PROGRAM 

CONTROLLER 

BIT 

MANIPULATION 

UNIT 

EOnCE / JTAG 

TAP 

INSTRUCTION 

DECODER 

INTERRUPT 

UNIT 

LOOPING 

UNIT 

A2 

B2 

C2 

D2 

A1 

B1 

C1 

D1 

Y0 

Y1 

X0 

MAC 

and ALU 





Mapping the Architecture to DSP Algorithms 

AGU ALU1 ALU2 

M 01 

N 3 

A0 

B0 

C0 

D0 

R0 

R1 

R2 

R3 

R4 

R5 

N 

SP 

DATA 

ALU 

Multi-bit 

Shifter 

XAB1 

XAB2 

PAB 

PDB 

CDBW 

CDBR 

XDB2 

Program 

Memory 

Data 

Memory 

IP-Bus 

Interface 

External 

Bus 

Interface 

14 

Operations Performed: 

• Multiply-Accumulate 

• 3 Memory Accesses 

• 2 Address Additions 

Instruction Fetch: 

PAB - 21 bits 

PDB - 16 bits 

1st Data Access: 


CDBR - 32 bits 

2nd Data Access: 


XDB2 - 16 bits 

TM

Pulse Width Modulation Modules 





15 

TM

Pulse Width Modulator (PWM) – MC56F800x, MC56F80xx 

► Clock PWM up to 96Mhz 

► Three complementary signal pairs or six independent 

signals or combinations 

► Complementary channel operation 

• Separate deadtime insertions for rising and falling edge 

• Separate top and bottom polarity control 

► Edge-aligned or center-aligned signals 

► 15-bits of resolution 

► Half-cycle reload capability 

► Asymmetric mode of operation (for phase shifting) 

► Programmable integral reload rates (half to 16) 

► Individually software-controlled PWM outputs 

► ADC synchronization 

► Up to 4 programmable fault inputs 

► PWM compare output polarity control 

► 8 or 4 mA current source/sink 

► Output polarity control 

► Write protected registers 

► Double-buffered PWM registers 

► Wait/debug mode operation 

► Selectable PWM supply source for each 

complementary PWM signal pair (F8000 family only) 

• PWM generator 

• External GPIO 

• Internal timer channel 

• ADC conversion result, taking into account values setting ADC 

high and low limit register 





16 

TM

Enhanced Flex Pulse Width Modulator (eFlexPWM) – 56F824x/5x 

► Four independent sub-modules with own time base, two PWM 

outputs + 1 auxiliary PWM input/output 

► 16 bits resolution for center, edge aligned, and asymmetrical 

PWMs 

► Fractional delay for enhanced resolution of the PWM period 

and edge placement 

► Complementary pairs or independent operation 

► Independent control of both edges for each PWM output 

► Synchronization to external hardware or other PWM submodules 

► Double buffered PWM registers 

► Integral reload rates from 1 to 16 include half cycle reload 

► Half cycle reload capability 

► Multiple output trigger events per PWM cycle 

► Support for double switching PWM outputs 

► Fault inputs can be assigned to control multiple PWM outputs 

► Programmable filters for fault inputs 

► Independently programmable PWM output polarity 

► Independent top and bottom deadtime insertion 

► Individual software control for each PWM output 

► Software control, and swap features via FORCE_OUT event 

► Compare/capture functions for unused PWM channels 

► Enhanced dual edge capture functionality 





17 

TM





eFlexPWM - Sub-Module Detail 

18 

TM





eFlexPWM – PWM Generation 

19 

TM

VAL1 ($0100) 

VAL5 

INIT ($FF00) 

($0000) 

VAL3 

VAL2, VAL4 = $FF00 

CH0 b 

CH0 a 





eFlexPWM – Edge Aligned PWM Generation 

► All PWM-on values are set to the init value, and never changed again. Positive PWM-off values 

generate pulse widths above 50% duty cycle . Negative PWM-off values generate pulse widths 

below 50% duty cycle . This works well for bipolar waveform generation. 

20 

TM

VAL1 ($0100) 

VAL3 

VAL5 

($0000) 

VAL4 

VAL2 

INIT ($FF00) 

Ch0 a 

Ch0 b 

eFlexPWM – Center Aligned PWM Generation 

► When the Init value is the signed negative of the Modulus value, the PWM module works in signed 

mode. Center-aligned operation is achieved when the turn-on and turn-off values are the same 

number, but just different signs. 





21 

TM

VAL1 ($0100) 

INIT ($FF00) 

VAL5 

VAL3 

($0000) 

VAL4 

VAL2 

CH0 a 

CH0 b 

► In this example, both PWMs have the same 

duty-cycle. However, the edges are shifted 

relative to each other by simply biasing the 

compare values of one waveform relative to 

the other. 





eFlexPWM – Shifted PWM Generation 

► Alternatively, if the waveforms are 

generated by different sub-modules, the 

waveforms can be shifted by simply 

changing the Init value of one sub-module 

relative to the other. 

22 

TM





eFlexPWM – Force Output Logic 

23 

TM

eFlexPWM – Complementary and Deadtime Logic 





24 

TM

eFlexPWM – Fractional Delay and Output Logic 





25 

TM

eFlexPWM – High Resolution Duty Cycle Generation 

►PWM resolution is given by input clock of PWM module 

►Example: 

• Let’s generate PWM signal with MODULO=4, DUTY_CYCLE=2 (50 %) 

0011 

0000 

t PWM 

t clk 





26 

TM


►PWM resolution is given by input clock of PWM module 

►The PWM resolution can be enhanced by analog delay circuit, which can 

place edge between two edges, derived from input clock 

►Example: 

• Consider 2-bit analog delay block 

• Let’s generate PWM signal with MODULO=4:0, DUTY_CYCLE=2:3 (68.75 %) 

0011:00 

0000:00 

t PWM 

t clk 





27 

TM


►At high resolution duty cycle generation 

• The leading edge is usually aligned with digital clock 

• The falling edge is generated by delay block 

• The analog delay is constant every PWM period 

0011:00 

0010:11 

0000:00 

t clk 

t timer 

t PWM 

0000:00 

PWM output using delay block 

DUTY_CYCLE = 0010:11 

0010:11 

0010:11 

0000:00 0000:00 

PWM output w/t delay block 

DUTY_CYCLE = 0010 





28 

Timer clock 

0010:11 

TM

►Example: 

0011 

0000 

eFlexPWM – High Resolution Frequency Generation 


• Let’s generate PWM signal with MODULO=4:2, DUTY_CYCLE=2:1 (50 %) 

t PWM 

t clk 





29 

TM

►Example: 

0011:00 

0000:00 



• Let’s generate PWM signal with MODULO=4:2, DUTY_CYCLE=2:1 (50 %) 

t PWM 

t clk 





30 

TM


►At high resolution frequency generation 

• Both edges are generated by delay block 

0011:00 

0010:01 

0010:00 

0001:00 

0000:10 

0000:00 

t clk 

• The analog delay is changing edge by edge every PWM period 

• The analog delay must be calculated every edge or requires some hardware 

support 

t timer 

t PWM 

0000:00 0010:01 0000:10 

0010:11 

0000:00 + 1clk 0010:01 

PWM output using delay block 

period = 0100:10 

PWM output w/t delay block 

period = 0100 





31 

Timer clock 

TM

► Need to calculate the 

next edge position for 

rising and falling 

edges within very 

short period 

► Software not fast 

enough, so need 

hardware adder 

► Diagram shows 21 bit 

adder to control both 

edges automatically 

setting new 

comparator values 

after each edge has 

been triggered 

eFlexPWM – HR Frequency Generation HW Support 

Ideal timing 

16 bits 

at IP Bus 

timing 

resolution 

5 bits 

NanoEdge 

timing 

resolution 

PWM 

Period N 

16 bit + 5 bit 

adder 





PWM Period N-1 

32 

16 bits 

at IP Bus 

timing 

resolution 

5 bits 

NanoEdge 

timing 

resolution 

5 bits from previous NEP calculation 

Actual timing Timer 

16 bits 

at IP Bus 

timing 

resolution 

5 bits 

NanoEdge 

timing 

resolution 

PWM 

Period N 

• PWM reload times are restricted to 16-bit IP bus timing 

(truncation of 21 bit value). Any residual left over from 

PWM period N-1 needs to be added back to period N. 

TM

eFlexPWM – HR Frequency Generation from User Perspective 

►The new edge calculation is seem less from user perspective 

►The user sets required 21-bit (16+5 bit) values into corresponding value 

registers only 

►The 5-bit delay block corresponds to 1.92 GHz input clock (for 60MHz 

PWM module input clock) 

16-bit digital value 

PWM Value Register 

NanoEdge TM placement not used. 16-bit value only. 


5-bit nanoedge 

value 

PWM Value Register PWM Fractional Value Register 

NanoEdge TM placement enabled. 21-bit (32-bit) value. 





33 

TM

eFlexPWM – HR Frequency Generation from User Perspective 

►Example of high resolution calculation 

• For high frequency the digital value is usually less than 11 bits. For example, 

200 kHz edge-aligned PWM has resolution less than 9 bits 

• Therefore we can keep calculation in 16 bits 

• Result of calculation is moved right by 5 bits and written into 32-bit register 


Internal User Representation 


value 



value 

PWM Value Register PWM Fractional Value Register 

NanoEdge TM placement enabled. 21-bit (32-bit) value. 





34 

TM

Analog to Digital Converters 





35 

TM

► Two ADC modules allowing 

parallel conversion 

► Input voltage range from VSSA to VDDA 

► Up to 28 analog inputs 

► Output in 12-, 10- or 8-bit 

right-justified format 

► Single or continuous conversion (automatic 

return to idle after single conversion) 

► 2.5 μs conversion time 

► Configurable sample time and conversion 

speed/power 

► Conversion complete flag and interrupt 

► Input clock selectable from up to 

four sources 

► Operation in wait or stop modes for lower 

noise operation 

► Asynchronous clock source for lower noise 

operation 

► Hardware and software triggering 

► Temperature sensors that are routed 

to ANA26 and ANB26 

► Support up to four samples per conversion 





A/D Converter – MC56F800x 

36 

TM

Programmable Gain Amplifier (PGA) – MC56F800x 

► Sampled PGA architecture 

► Common mode noise and offset cancelation 

► Synchronized with PWM operation 

► 0.14 MSPS maximum 

► Sampling time can be precisely controlled 

(to less than 0.1 μs) 

► Programmable gains (1×, 2×, 4×, 8×, 16×, 

and 32×) 

► Selectable tradeoff for slower/low power 

versus faster/more power 

► Rail-to-rail input voltage range 

► Single-ended output routed directly to on-chip 

ADCs ANA15 and ANB15 

► Software and hardware triggers are available 

► Includes additional calibration features: 

• Offset calibration eliminates any errors in the 

internal reference used to generate the 

VDDA/2 output center point 

• Gain calibration can be used to verify the 

gain of the overall datapath 

• Both features require software correction of 

the ADC result 





37 

TM

► 12-bit resolution 

► Maximum ADC clock frequency is 5.33 MHz 

► Sampling rate up to 1.6 million samples per second 

► Sequential: First 1.6μs subsequent 1.125μs 

► Simultaneous: 8 conversions in 4.97μs 

► Internal or external Vref 

► ADC can be synchronized to a PWM via the 

SYNC signal 

► High and low limits can control PWM outputs 

► Simultaneous or sequential sampling 

► Internal multiplexer to select two of eight inputs 

► Ability to sequentially scan and store up to eight 

measurements 

► Ability to simultaneously sample and hold 

two inputs 

► Optional interrupts at the end of a scan, if an 

out-of-range limit is exceeded, (high or low) or 

at zero crossing 

► Optional sample correction by subtracting a 

pre-programmed offset value 

► Signed or unsigned result 

► Single-ended or differential inputs for all input pins 

with support for an arbitrary mix of input types 

► Auto-standby mode to reduce power consumption 

► Power savings modes allow automatic 

shutdown/startup of all or part of ADC 






38 

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39 

TM

►Differences from 56F801x devices: 

• 16 sample and result registers 





A/D Converter – MC56F802x/3x 

• First 8 samples support high/low limits, zero-crossing and offset features only 

40 

TM

► Differences from 56F802x/3x devices: 

• ADC input clock 10 MHz (conversion 

time 850/600 ns) 

• Integrated PGA with gain 1x, 2x, 4x 

• Support multi-trigger operation 

AN0 

AN1 

… 

ANx 

Vrefl 

MUX 

Gain Setting 

X1, x2, x4 

PGA 





V+ 

V- 

12Bit 

ADC 

RESULT MUX 

A/D Converter – MC56F824x/5x 

8x 

8x 

Channel Select 

Single Ended or Differential 

HIGH 

LIMIT 

LOW 

LIMIT 

41 

> 

< 

Zero Crossing Logic 

ADC 

RESULT 

ADC 

OFFSET 

Above 

Below 

16x 

8x 

IRQ Logic 

IRQ 

TM

Analog Comparators 





42 

TM

CIN_A0 

CIN_A1 

CIN_A2 

DAC_A 

Export to 

CMP_B 

Import From 

CMP_B 

Export 

Source Select 

PSEL [0,2] 

ESEL [0,1] NSEL [0,2] 

M 

U 

X 

M 

U 

X 

Negative input 

Source Select 





M 

U 

X 

Analog Comparator – MC56F802x/3x 

Power Down 

+ 

- 

PDN 

INV 

CMP_A 0 

1 

43 

Programmable 

Glitch Filter 

Falling Edge 

Interrupt Request 

Rising Edge 

Interrupt Request 

COUT 

To Timer A1 

To PWM 

To GPIO 

To PWM Fault 1 

TM





Analog Comparator – MC56F802x/3x 

► Up to two continuous-time differential-input analog comparator modules 

► Internal switching matrix supports the independent connection of the analog inputs 

► to the positive or negative input of the analog comparator and to the comparator’s 

export output for another comparator module. 

► 5 selectable input sources: 

• Three GPIO pins 

• One DAC output 

• One import input from another comparator module 

► Programmable comparator output polarity 

► Comparator output edge indicator 

► Interrupt can be generated by comparator output rising edge, or falling edge, 

or both edges 

► Comparator output can be fed to timer input, PWM faults input, PWM source, 

external pin output 

► Software controlled power down mode 

44 

TM

► Operates over the entire supply range 

► Less than 40 mV of input offset 

► Less than 15 mV of hysteresis 

► Inputs may range from rail to rail 

► Selectable interrupt on rising edge, falling edge, 

or both edges of comparator output 

► Selectable inversion on comparator output 

Analog Comparator – MC56F800x, MC56F824x/5x 





► Two software selectable performance levels: 

• Shorter propagation delay at the expense 

of higher power 

• Low power, with longer propagation delay 

► Comparator output may be: 

• Sampled 

• Windowed (ideal for certain PWM 

zero-crossing-detection applications) 

• Digitally filtered 

• Filter can be bypassed 

45 

TM

Timers 





46 

TM

Primary Input 

Secondary Input 

INPUTS 

PRESCALER 

OTHER INPUTS 

CONTROL 

STATUS & 

CONTROL 

MUX 

Quad-Timer Channel 

COUNTER 

TMRLOAD TMRHOLD CAPTURE TMRCMP1 TMRCMP2 





COMPARATOR COMPARATOR 

DATA BUS 

Quad Timer – All DSCs 

MUX OFLAG 

CMPLD1 CMPLD2 

► Unique architecture with 2x Inputs (primary + secondary) and 1x output 

► Powerful MUX - primary input, secondary input and output can be connected to external pins 

► Individual channel capability - input capture trigger, output compare, clock source, prescaler 

► Counters are pre-loadable, count once or repeatedly 

► Master operation - any channel can be a master that broadcasts its compare signal to the other channels. This way 

they can be configured to reinitialize their counters and/or force their OFLAG output signals to predetermined values. 

► Compare - The TMRCMP1/2 registers provide the compare values (up/down) for the counter. If a match occurs, the 

OFLAG signal can be set, cleared, or toggled (polarity is selectable). If enabled, an interrupt is generated, and the new 

compare value is loaded into TMRCMP1 or 2 registers from TMRCMPLD1 and 2 (as enabled). 

► Capture register stores a copy of the counter’s value when an input edge (positive, negative, or both) is detected. 

Once a capture event occurs, no further updating of the capture register will occur until the input edge flag is cleared. 

47 

OUTPUT 

Output 

4x 

TM





Quad Timer Operating Modes 

►Stop Mode: Counter is inert. No counting will occur ►Count Mode: Counts rising or falling edges 

(generating periodic interrupts, timing purposes) 

►Edge Count Mode: Counts rising and falling edges 

(counting of simple encoder wheel) 

►Signed Count Mode: Counts primary input up or down 

based on polarity of secondary input 

►Gated Count Mode: Counts primary input if secondary 

input is high (signal width measurement) 

►Cascaded Count Mode: Input is connected to the 

output of another (great for large counts up to 2 64 ) 

48 

TM

►Triggered Count Mode: Start/Stop count of primary input on rising edge of secondary input. 






►One-Shot Mode: Provides timing delays 

(ADC acquisition of new samples until a specified period of time has passed since the PWM sync signal occurred) 

49 

TM

► Fixed Frequency PWM: Fixed frequency, variable 

duty cycle (driving PWM amplifiers) 

► Pulse Output Mode: Supports stepper motor 

systems and provides change of signal frequency 

and number of pulses 

Count Mode Timer is Off Timer is in Count Mode 

Primary 

Count 0 1 2 3 4 0 

Output 

Timer 

Stopped due 

to Compare 

(COMP1 = 4) 






► Variable Frequency PWM: Variable frequency 

and duty cycle (driving PWM amplifiers) 

► Quadrature Count Mode 

• Counter will decode the primary and secondary 

external inputs as quadrature encoded signals 

• Compare interrupts will signal commutation 

50 

TM

Others 





51 

TM

►Flexible signal interconnection 

among peripherals 

►Connects any of 22 signals on 

left side to the output on right 

side (multiplexer) 

►Total 30 multiplexers 

►All multiplexers share the same 

set of 22 signals 

►Increase flexibility of peripheral 

configuration according to user 

needs 





Crossbar Switch - MC56F824x/5x 

52 

TM

5-bit 

VREF 

12-bit DAC output 


X4 

TB[3:0] 

X9 

PWMA[3:0] 

PWMB[3:0] 

PWMX[3] 

X3 

0 

1 

2 

3 

3 

0 

2 

1 

Crossbar Inter-module Connection - MC56F824x/5x 

HSCMP 

Quad Timer B 

8-ch 

GHzPWM 

6 

OUT_TRIG0[2,0] 


14 

OR 

Functions 

2 OUT_TRIG0[3] 

OUT_TRIG1[3] 

Pin 

X6 





4 

4 

EXTA[3:0] 

EXT_SYNC[3:0] 

EXT_FORCE 

EXT_CLK 

FAULT[3:0] 

3 

3 

Window / 

Sample[2:0] 

4 

Crossbar 

Fabric 

X6 

Trigger[1:0] 

To comparators 

SYNC_IN 

I/O 

Muxing 

53 

Dual 

12bit ADC 

DAC input for test only 

12-bit DAC Output 

12-Bit 

DAC 

peripheral 

functions 

Pin 

ADC_In 

Pin 

Pin 

I/O Module 

Pin 

I/O Module 

TM

ADC to PWM Synchronization 





54 

TM

Why Is ADC to PWM Synchronization Needed? 

►ADC sampling helps to filter the measured current - antialiasing 

Average Current 

Sampled Current 

PWM 0 

ADC trigger Signal 

A/D 

calc. 

PWM Period 





Inductor Current 

Data Processing and New PWM Parameters Calculation 

55 

Asynchronous 

Sampling 

Synchronized 

Sampling 

TM

Why Is ADC to PWM Synchronization Needed? 

►Phase current can be sensed for certain time only 

+U/2 

-U/2 

PWM At 

PWM Ab 

Shunt 

resistor 

PWM Bt PWM Ct 

DC Bus 

Phase A Phase B Phase C 

PWM Bb PWM Cb 

Shunt 

resistor 

Ground 





n 

3-ph AC Induction Motor 

3-ph PM Synchronous Motor 

time to sensing 

stabilized 

56 

current 

sampling 

window 

PWM1 Q AT 

PWM2 Q AB 

I sense_A 

Dead 

Time 

TM

► Smart combination of the PWM + QTimer + 

ADC allows precise control of the 

sample event 

► The PWM synch output is connected to 

secondary input of QTimer - Ch3 

► The QTimer Ch3 output is connected to 

ADC SYNC0 

► The QTimer Ch2 output is connected to 

ADC SYNC1 

► The ADC sample can be easily synchronized 

with PWM with no software overhead 

(constant delay). Note the delay also can be 

applied to the external trigger signal 

► Cycle-by-cycle control of the QTimer 

addresses advanced ADC trigger 

delay control 





ADC to PWM Synchronization: MC56F80xx 

3 

57 

PWM Sync 

2 

1 

ADCA 

PWM 

MUX 

0 

ADC SYNC1 

ADCB 

IP BusCLK 

ADC SYNC0 * can be used to mimic 

ADC SYNC pulse during 

debugging 

* 

TM

► QTimer Ch3 settings: 

• Primary input: System clock 

• Secondary Input: 3-th input 

(PWM synch) 

• Operation mode: Triggered 

mode 

• Count length: Count until 

compare and reinitialize 

• Output mode: Clear on 

secondary, set on compare 

► t1 - time between PWM 

SYNC signal and TMR3 

output. TMR3 output starts 

ADC conversion 

immediately. 

► t2 – ADC conversion time 

ADC to PWM Synchronization Details: MC56F80xx 

PWM COUNTER 

PWM SYNC 

PWM 

GENERATOR 

OUTPUTS 0, 1 

PWM 

PINS 0, 1 

POWER 

STAGE 

VOLTAGE 

TMR3 

COUNTER 

TMR3 

OUTPUT 

ADC 

CONVERSION 





ADC 

ISR 

dead-time/2 

dead-time 

t1 

t2 

58 

dead-time/2 

dead-time 

TM





ADC to PWM Synchronization: MC56F800x 

59 

TM

Programmable Delay Block Operation Modes – MC56F800x 

► Individual Operation 

• Each ADC is controlled individually 

► ORed Operation 

• Both ADC converters operate in ping – pong 

mode. Up to four samples can be taken per 

conversion sequence 

► Pulsed (PWM) Operation 

• This mode can be used for window operation 

of high speed comparator 

• The output can be connected to pin and 

generated PWM signal 





60 

TM

ADC to PWM Synchronization: MC56F800x (Individual mode) 





61 

TM

ADC to PWM Synchronization: MC56F800x (ORed Mode) 





62 

TM

ADC to PWM Synchronization: MC56F800x (ORed Mode) 





63 

TM

5-bit 

VREF 



X4 

TB[3:0] 

X9 

PWMA[3:0] 

PWMB[3:0] 

PWMX[3] 

X3 

0 

1 

2 

3 

3 

0 

2 

1 

HSCMP 

Quad Timer B 

8-ch 

GHzPWM 

6 

ADC to PWM Synchronization: MC56F824x/5x 



14 

OR 

Functions 

2 OUT_TRIG0[3] 

OUT_TRIG1[3] 

Pin 

X6 





4 

4 

EXTA[3:0] 

EXT_SYNC[3:0] 

EXT_FORCE 

EXT_CLK 

FAULT[3:0] 

3 

3 

Window / 

Sample[2:0] 

4 

Crossbar 

Fabric 

X6 

Trigger[1:0] 

To comparators 

SYNC_IN 

I/O 

Muxing 

64 

Dual 

12-bit ADC 

DAC input for test only 

12-bit DAC Output 

12-Bit 

DAC 

peripheral 

functions 

Pin 

ADC_In 

Pin 

Pin 

I/O Module 

Pin 

I/O Module 

TM





eFlexPWM – PWM Generation 

65 

TM

8-ch eFlexPWM 

submodule 0 

submodule 1 

submodule 2 

submodule 3 

ADC to PWM Synchronization Details: MC56F824x/5x 

OUT_TRIG0[0] 

OUT_TRIG1[0] 

OUT_TRIG0[1] 

OUT_TRIG1[1] 

OUT_TRIG0[2] 

OUT_TRIG1[2] 

OUT_TRIG0[3] 

OUT_TRIG1[3] 

OR 

OR 

OR 





OR 

crossbar input[16] 


66 

crossbar 

input[19] 




Crossbar 

Fabric 

TM

Low Cost Current Measurement - 

Single Shunt Current Reconstruction 





67 

TM

+U/2 

-U/2 

PWM At 

PWM Ab 

Shunt 

resistor 





Single Shunt Current Reconstruction 

PWM Bt PWM Ct 


PWM Bb PWM Cb 

Shunt 

resistor 

n 

3-ph AC Induction Motor 

3-ph PM Synchronous Motor 

68 

DC Bus 

Ground 

TM

(000) (100) (110) (111) 

A 

B 

C 

i DC =0 

i DC =+i a 

i DC =-i c 

i DC =0 

(110) (100) 

i DC =-i c 

i DC =+i a 

Single Shunt Current Reconstruction - Analysis 

t = t + t 

deadtime 

progdelay 





delay 

► Measurement Table 

Voltage Vector DC-Link current i dc 

V 1 (100) +i a 

V 2 (110) -i c 

V 3 (010) +i b 

V 4 (011) -i a 

V 5 (001) +i c 

V 6 (101) -i b 

V 7 (111) 0 

V 0 (000) 0 

69 

TM

►Two current samples cannot be taken: 

Single Shunt Current Reconstruction - Issues 

1. Voltage vector is crossing a sector border 

• Only one sample can be taken 

2. Low modulation indexes 

• Sampling intervals too short 

• None of current samples can be taken 

Passing Active Vector 





Low Modulation Index 

70 

TM

►Asymmetrical PWMs 

• Case 1 – Passing active vector: 

� Freeze center edge 

� Move one critical edge 

� Goes for higher modulation indexes 

Single Shunt Current Reconstruction - Solution 

• Case 2 – Low modulation indexes: 

� Freeze center edge 

� Move both side edges in opposite direction 

� Goes for low modulation indexes 





71 

Critical edge 

Move critical edge 

Critical edges 

Move critical edges 

TM

PWM Modulo Counter 

Compare level sample #2 



Timer ch. 3 Counter 

ADC Conversion 

ADC End-of-Scan ISR 

PWM Reload ISR 

Single Shunt Current Reconstruction – MC56F8013 

Implementation 





Conversion time 

each 2.48us 

ISR duration 

each 0.92us 

72 

ISR duration 

cca. 13.8us 

TM

BLDC Motor Commutation 





73 

TM

►Six Step BLDC Motor Control 

• Voltage applied on two phases only 

+U/2 

-U/2 

PWM At 

PWM Ab 

Shunt 

resistor 

PWM Bt PWM Ct 


PWM Bb PWM Cb 

Shunt 

resistor 





n 

3-ph Brushless DC Motor 


DC Bus 

Ground 

74 

TM

►Six Step BLDC Motor Control 

• Voltage applied on two phases only 

• It creates 6 flux vectors 

• Phases are powered based on rotor position 

• The process is called commutation 

Phase voltages 






75 

TM

►Complementary bipolar PWM switching 






Q1=Q4=PWM; Q2=Q3=Q1 

76 

TM

70% 

1. 

30% 

2. 

BLDC Motor Commutation – MC56F800x, MC56F80xx 

A B C 

70% 

3. 

30% 

4. 

70% 





5. 

30% 

6. 

PWM Channel Control Register 

MASK 

0 0 0 0 0 0 

0 0 0 

One “shot” write to all six 

PWM channels! 

Value written to this register 

defines just the speed of 

motor rotation and 


0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 

5999h ≈ 70% of max. value of Duty Cycle 

when 7FFFh is the max. value 

77 

SWAP 

TM

0% 

1. 

0% 

2. 


A B C 

70% 

3. 

30% 

4. 

70% 





5. 

30% 

6. 


MASK 

0 0 0 0 1 1 

0 0 0 

6. 5. 4. 3. 2. 1. 

transistors 

Mask will disable 

the complementary 

transistor pair 


MASK 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 



78 

SWAP 

TM

0% 

1. 

0% 

2. 


Mask and Swap are set simultaneously! 

Value written to this register defines the 

exact commutation stage. 

A B C 

70% 30% 

3. 

4. 

SWAP 





5. 

30% 70% 

6. 


MASK 


79 

SWAP 

0 0 0 0 1 1 

0 0 1 

6. 5. 4. 3. 2. 1. 

transistors 

Swap reroutes the top 

and bottom control 

signals of complementary 

pair 

C B A 

phases 

0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 



TM

►Advantage: 


• The MASK and SWAP feature is asynchronous to PWM generation 

• Speed control and commutation control are fully independent 

►The same approach can be used on 56F82xx using FORCE_OUT logic 

►The 56F82xx allows preloading of new state and time for next 

commutation. The commutation is performed based on timer event 





80 

TM

Motor Control and Energy Conversion Demos 





81 

TM

► Six step commutation 

► Sensorless back-EMF zero 

crossing detection technique 

► Back-EMF zero crossing 

detection using internal 

comparators 

► Running on MC9S08MP16 

► Both directions of rotation 

► Speed closed loop control 

► Torque closed loop control 

► Target applications: 

• Fans 

• Compressors 

• Pumps 

• Appliances 

Sensorless BLDC Motor Control Using MC9S08MP16 





82 

TM

► MC56F80xx digital signal controller 

► 3-phase AC/BLDC high voltage 

power stage board 

► 1-phase line input 110/230VAC @ 

50/60Hz 

► Appliance PM motor 

► Initial rotor position detection 

► Full torque at motor start-up 

► Field weakening 

► Application based on C-callable 

library functions (GFLIB, GDFLIB, 

MCLIB, ACLIB) 

► Current control loop execution 

time: 55us 

► Speed control loop with field 

weakening execution time : 17us 

► Flash: ~ 6KB, RAM ~ 1.5KB 

► Reference design manual 

Sensorless PMSM Motor Control Using MC56F80xx 





83 

TM

► 500W digitally controlled LLC 

resonant converter 

► Input voltage 

• 85-265Vac @ 45-65Hz 

► Output voltage 

• 12V/41 Amps (max.) 

• 5V/25 Amps (max.) 

► Output power 

• 500W shared by both voltage outputs. 

The power limit can be set individually 

by SW for each voltage output. 

► Communication 

• PM bus communication (HW ready) 

• CAN communication (HW ready) 

• Communication with PC using USB 

► Full fault protection 

• Over-voltage, over-current, overtemperature 

on both primary and 

secondary side. Active controlled cooling 





AC/DC Switch Mode Power Supply 

84 

TM

► 400 VA digitally controlled solar inverter 

► One or two 200Wp solar panels 

► On grid/off grid operation 

► Single phase output 230V/50Hz or 115V/60Hz 

► Optional battery charger 

► MPPT algorithm implemented 

► Over-current, short circuit, input under-voltage protection 





Solar Inverter using MC56F8023 

85 

TM

eFlexPWM - Freescale Semiconductor

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