Cache Usage Tutorial - MGNet

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CPU trendsEPIC (similar to VLIW) (IA64)Multi-threaded architectures (Alpha, Pentium4HT) Multiple CPUs on a single chip (IBM Power 4)Within the next decade• Billion transistor CPUs (today 200 milliontransistors)• Potential to build TFLOPS on a chip (e.g., SUNgraphics processors)• But no way to move the data in and out sufficientlyquickly!Prof. Craig C. DouglasUniversity of Kentucky andYale UniversityHiPC2003, 12/17/2003 vHPC <strong>Cache</strong> Aware Methods 12
Memory wallLatency: time for memory to respond to a read (orwrite) request is too long• CPU ~ 0.5 ns (light travels 15cm in vacuum)• Memory ~ 50 nsBandwidth: number of bytes which can be read(written) per second• CPUs with 1 GFLOPS peak performancestandard: needs 24 Gbyte/sec bandwidth• Present CPUs have peak bandwidth
Page 4 and 5: Part IArchitectures and Fundamental
Page 6 and 7: How fast should a solver be?(just a
Page 8 and 9: Comparison of solvers(what got me s
Page 10 and 11: PipeliningProf. Craig C. DouglasUni
Page 14 and 15: Memory acceleration techniquesInter
Page 16 and 17: CachesFast but small extra memoryHo
Page 18 and 19: Cache issuesUniqueness and transpar
Page 20 and 21: Effect of cache hit ratioThe cache
Page 22 and 23: Cache organizationNumber of cache l
Page 24 and 25: Typical architectures IBM Power 3:
Page 26 and 27: Basic efficiency guidelinesChoose t
Page 28 and 29: Choose the best algorithm(cont‘d)
Page 30 and 31: Sources for librariesVendor-indepen
Page 32 and 33: Find good compiler optionsModern co
Page 34 and 35: Use suitable data layoutAccess memo
Page 36 and 37: ProfilingSubroutine-level profiling
Page 38 and 39: Profiling: hardware performancecoun
Page 40 and 41: Profiling tools: valgrindMemory/thr
Page 42 and 43: Profiling tools: PAPIPAPI = Perform
Page 44 and 45: hpcview Screen ShotProf. Craig C. D
Page 46 and 47: HPCToolkit Philosophy 2Provide info
Page 48 and 49: Our reference code2D structured mul
Page 50 and 51: Using PCL - Example 1Digital PWS 50
Page 52 and 53: Using PCL - Example 2PCLinit(&descr
Page 54 and 55: Examples of DCPI toolsdcpiwhatcg: W
Page 56 and 57: Using DCPI - Example 2Call the DCPI
Page 58 and 59: Using DCPI - Example 2Static stalls
Page 60 and 61: Part IIOptimization TechniquesforSt
Page 62 and 63:
Optimization ofFloating-PointOperat
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Loop unrollingSimplest effect of lo
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Loop unrolling:Improving flop/load
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Fused Multiply-Add (FMA)On many CPU
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Exposing ILP (cont’d)Superscalar
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AliasingArrays (or other data) that
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Aliasing (cont’d)Aliasing is lega
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Eliminating overheads:if statements
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Eliminating loop overheadsFor start
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Eliminating subroutine callingoverh
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Data layout optimizationsArray tran
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Data layout optimizationsStride-1 a
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Data layout optimizations:Cache-awa
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Data layout optimizations:Array pad
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Data layout optimizations:Array pad
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Loop optimizationsLoop unrolling (s
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Data access optimizations:Loop fusi
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Data access optimizations:Loop spli
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Data access optimizations:Loop bloc
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Data access optimizations:Loop bloc
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Data access optimizationsLoop block
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Two common multigridalgorithmsV Cyc
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DiMEPACK libraryC++ interface, fast
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Example:Cache-OptimizedMultigrid on
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Data layout optimizationsfor 3D mul
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Data layout optimizationsfor 3D mul
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Data access optimizationsfor 3D mul
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Example:Cache Optimizations forthe
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LBM (cont‘d)Stream: read distribu
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Layout 2: Grid Compression: save me
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3-way blocking (cont’d):Prof. Cra
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4-way blocking (cont’d):Prof. Cra
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Layout: Grid compression, access pa
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Performance resultsMFLOPS for 2D GS
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Memory access behaviorStandard impl
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Memory access behavior2D skewed blo
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Performance results (cont’d)2D LB
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Performance results (cont’d)3D LB
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C++-specific considerationsWe will
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Inlining (cont‘d)Advantages:• R
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Inlining virtual functionsVirtual f
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ExampleDefine a simple vector class
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Example (cont‘d)Need a wrapper cl
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Example (cont‘d)Need overloaded o
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Part IIIOptimization Techniques for
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Is It really unstructured?This is r
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Motivating example• Suppose probl
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Cache aware Gauss-SeidelPreprocessi
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Example of subblock membershipCache
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Standard Gauss-SeidelThe complexity
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Cache boundaries connectedProf. Cra
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Physical boundaries unknownProf. Cr
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Physical boundaries knownProf. Crai
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Physical boundaries knownThe comple
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Preprocessing costsPessimistic (nev
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Numerical experiments: BavariaExper
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Implementation detailsOne parameter
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Journal articles C.C. Douglas, Cach
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Conference proceedingsC. Weiss, W.
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Cache Usage Tutorial - MGNet

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