Cache Usage Tutorial - MGNet

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Physical boundaries knownProf. Craig C. DouglasUniversity of Kentucky andYale UniversityHiPC2003, 12/17/2003 vHPC <strong>Cache</strong> Aware Methods 172
Physical boundaries knownProf. Craig C. DouglasUniversity of Kentucky andYale UniversityHiPC2003, 12/17/2003 vHPC <strong>Cache</strong> Aware Methods 173
Page 4 and 5:
Part IArchitectures and Fundamental
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How fast should a solver be?(just a
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Comparison of solvers(what got me s
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PipeliningProf. Craig C. DouglasUni
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CPU trendsEPIC (similar to VLIW) (I
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Memory acceleration techniquesInter
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CachesFast but small extra memoryHo
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Cache issuesUniqueness and transpar
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Effect of cache hit ratioThe cache
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Cache organizationNumber of cache l
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Typical architectures IBM Power 3:
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Basic efficiency guidelinesChoose t
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Choose the best algorithm(cont‘d)
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Sources for librariesVendor-indepen
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Find good compiler optionsModern co
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Use suitable data layoutAccess memo
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ProfilingSubroutine-level profiling
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Profiling: hardware performancecoun
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Profiling tools: valgrindMemory/thr
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Profiling tools: PAPIPAPI = Perform
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hpcview Screen ShotProf. Craig C. D
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HPCToolkit Philosophy 2Provide info
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Our reference code2D structured mul
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Using PCL - Example 1Digital PWS 50
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Using PCL - Example 2PCLinit(&descr
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Examples of DCPI toolsdcpiwhatcg: W
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Using DCPI - Example 2Call the DCPI
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Using DCPI - Example 2Static stalls
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Part IIOptimization TechniquesforSt
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Optimization ofFloating-PointOperat
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Loop unrollingSimplest effect of lo
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Loop unrolling:Improving flop/load
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Fused Multiply-Add (FMA)On many CPU
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Exposing ILP (cont’d)Superscalar
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AliasingArrays (or other data) that
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Aliasing (cont’d)Aliasing is lega
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Eliminating overheads:if statements
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Eliminating loop overheadsFor start
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Eliminating subroutine callingoverh
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Data layout optimizationsArray tran
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Data layout optimizationsStride-1 a
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Data layout optimizations:Cache-awa
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Data layout optimizations:Array pad
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Data layout optimizations:Array pad
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Loop optimizationsLoop unrolling (s
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Data access optimizations:Loop fusi
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Data access optimizations:Loop spli
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Data access optimizations:Loop bloc
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Data access optimizations:Loop bloc
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Data access optimizationsLoop block
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Two common multigridalgorithmsV Cyc
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DiMEPACK libraryC++ interface, fast
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Example:Cache-OptimizedMultigrid on
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Data layout optimizationsfor 3D mul
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Data layout optimizationsfor 3D mul
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Data access optimizationsfor 3D mul
Page 122 and 123: Example:Cache Optimizations forthe
Page 124 and 125: LBM (cont‘d)Stream: read distribu
Page 126 and 127: Layout 2: Grid Compression: save me
Page 128 and 129: 3-way blocking (cont’d):Prof. Cra
Page 130 and 131: 4-way blocking (cont’d):Prof. Cra
Page 132 and 133: Layout: Grid compression, access pa
Page 134 and 135: Performance resultsMFLOPS for 2D GS
Page 136 and 137: Memory access behaviorStandard impl
Page 138 and 139: Memory access behavior2D skewed blo
Page 140 and 141: Performance results (cont’d)2D LB
Page 142 and 143: Performance results (cont’d)3D LB
Page 144 and 145: C++-specific considerationsWe will
Page 146 and 147: Inlining (cont‘d)Advantages:• R
Page 148 and 149: Inlining virtual functionsVirtual f
Page 150 and 151: ExampleDefine a simple vector class
Page 152 and 153: Example (cont‘d)Need a wrapper cl
Page 154 and 155: Example (cont‘d)Need overloaded o
Page 156 and 157: Part IIIOptimization Techniques for
Page 158 and 159: Is It really unstructured?This is r
Page 160 and 161: Motivating example• Suppose probl
Page 162 and 163: Cache aware Gauss-SeidelPreprocessi
Page 164 and 165: Example of subblock membershipCache
Page 166 and 167: Standard Gauss-SeidelThe complexity
Page 168 and 169: Cache boundaries connectedProf. Cra
Page 170 and 171: Physical boundaries unknownProf. Cr
Page 174 and 175: Physical boundaries knownThe comple
Page 176 and 177: Preprocessing costsPessimistic (nev
Page 178 and 179: Numerical experiments: BavariaExper
Page 180 and 181: Implementation detailsOne parameter
Page 182 and 183: Journal articles C.C. Douglas, Cach
Page 184 and 185: Conference proceedingsC. Weiss, W.
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