Cache Usage Tutorial - MGNet

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Loop unrollingSimplest effect of loop unrolling: fewer test/jumpinstructions (fatter loop body, less loop overhead)Fewer loads per flopMay lead to threaded code that uses multiple FPunits concurrently (instruction-level parallelism)How are loops handled that have a trip count that isnot a multiple of the unrolling factor?Very long loops may not benefit from unrolling(instruction cache capacity!)Very short loops may suffer from unrolling or benefitstronglyProf. Craig C. DouglasUniversity of Kentucky andYale UniversityHiPC2003, 12/17/2003 vHPC <strong>Cache</strong> Aware Methods 64
Loop unrolling: Making fatter loop bodiesdo i=1,Na(i)= a(i)+b(i)*cenddoii= imod(N,4)do i= 1,iia(i)= a(i)+b(i)*cenddodo i= 1+ii,N,4a(i)= a(i)+b(i)*ca(i+1)= a(i+1)+b(i+1)*ca(i+2)= a(i+2)+b(i+2)*ca(i+3)= a(i+3)+b(i+3)*cenddoExample: DAXPY operationdo i= 1,N,4a(i)= a(i)+b(i)*ca(i+1)= a(i+1)+b(i+1)*ca(i+2)= a(i+2)+b(i+2)*ca(i+3)= a(i+3)+b(i+3)*cenddoPreconditioning loop handlescases when N is not a multiple of 4Prof. Craig C. DouglasUniversity of Kentucky andYale UniversityHiPC2003, 12/17/2003 vHPC <strong>Cache</strong> Aware Methods 65
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Part IArchitectures and Fundamental
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How fast should a solver be?(just a
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Comparison of solvers(what got me s
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PipeliningProf. Craig C. DouglasUni
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CPU trendsEPIC (similar to VLIW) (I
Page 14 and 15: Memory acceleration techniquesInter
Page 16 and 17: CachesFast but small extra memoryHo
Page 18 and 19: Cache issuesUniqueness and transpar
Page 20 and 21: Effect of cache hit ratioThe cache
Page 22 and 23: Cache organizationNumber of cache l
Page 24 and 25: Typical architectures IBM Power 3:
Page 26 and 27: Basic efficiency guidelinesChoose t
Page 28 and 29: Choose the best algorithm(cont‘d)
Page 30 and 31: Sources for librariesVendor-indepen
Page 32 and 33: Find good compiler optionsModern co
Page 34 and 35: Use suitable data layoutAccess memo
Page 36 and 37: ProfilingSubroutine-level profiling
Page 38 and 39: Profiling: hardware performancecoun
Page 40 and 41: Profiling tools: valgrindMemory/thr
Page 42 and 43: Profiling tools: PAPIPAPI = Perform
Page 44 and 45: hpcview Screen ShotProf. Craig C. D
Page 46 and 47: HPCToolkit Philosophy 2Provide info
Page 48 and 49: Our reference code2D structured mul
Page 50 and 51: Using PCL - Example 1Digital PWS 50
Page 52 and 53: Using PCL - Example 2PCLinit(&descr
Page 54 and 55: Examples of DCPI toolsdcpiwhatcg: W
Page 56 and 57: Using DCPI - Example 2Call the DCPI
Page 58 and 59: Using DCPI - Example 2Static stalls
Page 60 and 61: Part IIOptimization TechniquesforSt
Page 62 and 63: Optimization ofFloating-PointOperat
Page 66 and 67: Loop unrolling:Improving flop/load
Page 68 and 69: Fused Multiply-Add (FMA)On many CPU
Page 70 and 71: Exposing ILP (cont’d)Superscalar
Page 72 and 73: AliasingArrays (or other data) that
Page 74 and 75: Aliasing (cont’d)Aliasing is lega
Page 76 and 77: Eliminating overheads:if statements
Page 78 and 79: Eliminating loop overheadsFor start
Page 80 and 81: Eliminating subroutine callingoverh
Page 82 and 83: Data layout optimizationsArray tran
Page 84 and 85: Data layout optimizationsStride-1 a
Page 86 and 87: Data layout optimizations:Cache-awa
Page 88 and 89: Data layout optimizations:Array pad
Page 90 and 91: Data layout optimizations:Array pad
Page 92 and 93: Loop optimizationsLoop unrolling (s
Page 94 and 95: Data access optimizations:Loop fusi
Page 102 and 103: Data access optimizations:Loop spli
Page 104 and 105: Data access optimizations:Loop bloc
Page 106 and 107: Data access optimizations:Loop bloc
Page 108 and 109: Data access optimizationsLoop block
Page 110 and 111: Two common multigridalgorithmsV Cyc
Page 112 and 113: DiMEPACK libraryC++ interface, fast
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Example:Cache-OptimizedMultigrid on
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Data layout optimizationsfor 3D mul
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Data layout optimizationsfor 3D mul
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Data access optimizationsfor 3D mul
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Example:Cache Optimizations forthe
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LBM (cont‘d)Stream: read distribu
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Layout 2: Grid Compression: save me
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3-way blocking (cont’d):Prof. Cra
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4-way blocking (cont’d):Prof. Cra
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Layout: Grid compression, access pa
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Performance resultsMFLOPS for 2D GS
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Memory access behaviorStandard impl
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Memory access behavior2D skewed blo
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Performance results (cont’d)2D LB
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Performance results (cont’d)3D LB
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C++-specific considerationsWe will
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Inlining (cont‘d)Advantages:• R
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Inlining virtual functionsVirtual f
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ExampleDefine a simple vector class
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Example (cont‘d)Need a wrapper cl
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Example (cont‘d)Need overloaded o
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Part IIIOptimization Techniques for
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Is It really unstructured?This is r
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Motivating example• Suppose probl
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Cache aware Gauss-SeidelPreprocessi
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Example of subblock membershipCache
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Standard Gauss-SeidelThe complexity
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Cache boundaries connectedProf. Cra
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Physical boundaries unknownProf. Cr
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Physical boundaries knownProf. Crai
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Physical boundaries knownThe comple
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Preprocessing costsPessimistic (nev
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Numerical experiments: BavariaExper
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Implementation detailsOne parameter
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Journal articles C.C. Douglas, Cach
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Conference proceedingsC. Weiss, W.
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Cache Usage Tutorial - MGNet

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