24AA01/02

M24AA01/021K 1.8V I 2 C Serial EEPROMFEATURESPACKAGE TYPES• Single supply with operation down to 1.8V• Low power CMOS technology- 1 mA active current typical- 10 µA standby current typical at 5.5V- 3 µA standby current typical at 1.8V• Organized as a single block of 128 bytes (128 x 8)or 256 bytes (256 x 8)• 2-wire serial interface bus, I 2 C compatible• Schmitt trigger, filtered inputs for noise suppression• Output slope control to eliminate ground bounce• 100 kHz (1.8V) and 400 kHz (5V) compatibility• Self-timed write cycle (including auto-erase)• Page-write buffer for up to 8 bytes• 2 ms typical write cycle time for page-write• Hardware write protect for entire memory• Can be operated as a serial ROM• ESD protection > 3,000V• 1,000,000 ERASE/WRITE cycles guaranteed• Data retention > 200 years• 8-pin DIP or SOIC package• Available for extended temperature rangesPDIPA0A1A2VSSSOICA0A1A2VSS1234123424AA01/0224AA01/0287658765VCCWPSCLSDAVCCWPSCLSDA- Commercial (C): 0°C to +70°C- Industrial (I): -40°C to +85°CDESCRIPTIONBLOCK DIAGRAMThe Microchip Technology Inc. 24AA01 and 24AA02are 1K bit and 2K bit Electrically Erasable PROMs. Thedevices are organized as a single block of 128 x 8-bitor 256 x 8-bit memory with a two wire serial interface.Low-voltage design permits operation down to 1.8 voltswith standby and active currents of only 3 µA and 1 mA,respectively. The 24AA01 and 24AA02 also have pagewritecapability for up to 8 bytes of data. The 24AA01and 24AA02 are available in the standard 8-pin DIPand 8-pin surface mount SOIC packages.I/OCONTROLLOGICSDASCLWPMEMORYCONTROLLOGICXDECHV GENERATOREEPROMARRAYPAGE LATCHESYDECVCCVSSSENSE AMPR/W CONTROLI 2 C is a trademark of Philips Corporation© 1998 Microchip Technology Inc. DS21052H-page 1

24AA01/021.0 ELECTRICALCHARACTERISTICS1.1 Maximum Ratings*VCC...................................................................................7.0VAll inputs and outputs w.r.t. VSS ................-0.6V to VCC +1.0VStorage temperature .....................................-65°C to +150°CAmbient temp. with power applied.............. -65°C to +125°CCSoldering temperature of leads (10 seconds) .............+300°CESD protection on all pins..................................................≥ 4 kV*Notice: Stresses above those listed under “Maximum ratings”may cause permanent damage to the device. This is a stress ratingonly and functional operation of the device at those or anyother conditions above those indicated in the operational listingsof this specification is not implied. Exposure to maximum ratingconditions for extended periods may affect device reliability.TABLE 1-1:NamePIN FUNCTION TABLEFunctionVSSGroundSDASerial Address/Data/I/OSCLSerial ClockWPWrite Protect InputVCC +1.8V to 5.5V Power SupplyA0, A1, A2 No Internal ConnectionTABLE 1-2:DC CHARACTERISTICSVCC = +1.8V to +5.5VCommercial (C):Tamb = 0°C to +70°CIndustrial (I): Tamb = -40°C to +85°CParameter Symbol Min Typ Max Units ConditionsWP, SCL and SDA pins:High level input voltageLow level input voltageHysteresis of Schmitt triggerinputsLow level output voltageVIHVILVHYS.7 VCC—.05 VDDVOL — — .40 VInput leakage current ILI -10 — 10 µA VIN = .1V to 5.5VOutput leakage current ILO -10 — 10 µA VOUT = .1V to 5.5VPin capacitance(all inputs/outputs)Operating currentCIN,COUTICC WriteICC Read————.3 VCC—VVV(Note)IOL = 3.0 mA, VCC = 1.8V— — 10 pF Vcc = 5.0V (Note 1)Tamb = 25˚C, FLCK = 1 MHz————Standby current ICCS ————0.5—0.05Note:This parameter is periodically sampled and not 100% tested.——33—1—10030—mAmAmAmAµAµAµAVCC = 5.5V, SCL = 400 kHzVCC = 1.8V, SCL = 100 kHzVCC = 5.5V, SCL = 400 kHzVCC = 1.8V, SCL = 100 kHzVCC = 5.5V, SDA = SCL = VCCVCC = 3.0V, SDA = SCL = VCCVCC = 1.8V, SDA = SCL = VCCWP = VSSFIGURE 1-1:BUS TIMING START/STOPVHYSSCLSDATSU:STATHD:STATSU:STOSTARTSTOPDS21052H-page 2© 1998 Microchip Technology Inc.

24AA01/02TABLE 1-3:ParameterAC CHARACTERISTICSSymbolStandard ModeMin Max Min MaxVCC = 4.5 - 5.5VFast Mode Units RemarksClock frequency FCLK — 100 — 400 kHzClock high time THIGH 4000 — 600 — nsClock low time TLOW 4700 — 1300 — nsSDA and SCL rise time TR — 1000 — 300 ns (Note 1)SDA and SCL fall time TF — 300 — 300 ns (Note 1)START condition hold time THD:STA 4000 — 600 — ns After this period the firstclock pulse is generatedSTART condition setuptimeTSU:STA 4700 — 600 — ns Only relevant for repeatedSTART conditionData input hold time THD:DAT 0 — 0 — ns (Note 2)Data input setup time TSU:DAT 250 — 100 — nsSTOP condition setup time TSU:STO 4000 — 600 — nsOutput valid from clock TAA — 3500 — 900 ns (Note2)Bus free time TBUF 4700 — 1300 — ns Time the bus must be freebefore a new transmissioncan startOutput fall time from VIH TOF — 250 20 +0.1 250 ns (Note 1), CB ≤ 100 pFmin to VIL maxCBInput filter spike suppressionTSP — 50 — 50 ns (Note 3)(SDA and SCL pins)Write cycle time TWR — 10 — 10 ms Byte or Page modeEndurance — 1M — 1M — cycles 25°C, Vcc = 5.5V, BlockMode (Note 4)Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improvednoise spike suppression. This eliminates the need for a TI specification for standard operation.4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application,please consult the Total Endurance Model which can be obtained on our BBS or website.FIGURE 1-2:BUS TIMING DATATFTRTHIGHTLOWSCLSCLINTSU:STATSPTHD:STATHD:DAT TSU:DAT TSU:STOTAATHD:STATAATBUFSDAOUT© 1998 Microchip Technology Inc. DS21052H-page 3

24AA01/022.0 FUNCTIONAL DESCRIPTIONThe 24AA01/02 supports a bi directional 2-wire busand data transmission protocol. A device that sendsdata onto the bus is defined as transmitter, and adevice receiving data as receiver. The bus has to becontrolled by a master device which generates theserial clock (SCL), controls the bus access, and generatesthe START and STOP conditions, while the24AA01/02 works as slave. Both, master and slave canoperate as transmitter or receiver but the master devicedetermines which mode is activated.3.0 BUS CHARACTERISTICSThe following bus protocol has been defined:• Data transfer may be initiated only when the busis not busy.• During data transfer, the data line must remainstable whenever the clock line is HIGH. Changesin the data line while the clock line is HIGH will beinterpreted as a START or STOP condition.Accordingly, the following bus conditions have beendefined (Figure 3-1).3.1 Bus not Busy (A)Both data and clock lines remain HIGH.3.2 Start Data Transfer (B)A HIGH to LOW transition of the SDA line while theclock (SCL) is HIGH determines a START condition.All commands must be preceded by a START condition.3.3 Stop Data Transfer (C)A LOW to HIGH transition of the SDA line while theclock (SCL) is HIGH determines a STOP condition. Alloperations must be ended with a STOP condition.3.4 Data Valid (D)The state of the data line represents valid data when,after a START condition, the data line is stable for theduration of the HIGH period of the clock signal.The data on the line must be changed during the LOWperiod of the clock signal. There is one clock pulse perbit of data.Each data transfer is initiated with a START conditionand terminated with a STOP condition. The number ofthe data bytes transferred between the START andSTOP conditions is determined by the master deviceand is theoretically unlimited, although only the last 16will be stored when doing a write operation. When anoverwrite does occur it will replace data in a first in firstout fashion.3.5 AcknowledgeEach receiving device, when addressed, is obliged togenerate an acknowledge after the reception of eachbyte. The master device must generate an extra clockpulse which is associated with this acknowledge bit.Note: The 24AA01/02 does not generate anyacknowledge bits if an internal programmingcycle is in progress.The device that acknowledges, has to pull down theSDA line during the acknowledge clock pulse in such away that the SDA line is stable LOW during the HIGHperiod of the acknowledge related clock pulse. Ofcourse, setup and hold times must be taken intoaccount. A master must signal an end of data to theslave by not generating an acknowledge bit on the lastbyte that has been clocked out of the slave. In thiscase, the slave must leave the data line HIGH to enablethe master to generate the STOP condition.FIGURE 3-1:DATA TRANSFER SEQUENCE ON THE SERIAL BUSDSCLorMSCL(A) (B) (D) (D) (C) (A)DSCLorMSCLSTARTCONDITIONADDRESS ORACKNOWLEDGEVALIDDATAALLOWEDTO CHANGESTOPCONDITIONDS21052H-page 4© 1998 Microchip Technology Inc.

24AA01/023.6 Device AddressThe 24AA01/02 are software-compatible with olderdevices such as 24C01A, 24C02A, 24LC01, and24LC02. A single 24AA02 can be used in place of two24LC01's, for example, without any modifications tosoftware. The “chip select” portion of the control bytebecomes a don't care.After generating a START condition, the bus mastertransmits the slave address consisting of a 4-bit devicecode (1010) for the 24AA01/02, followed by three don'tcare bits.The eighth bit of slave address determines if the masterdevice wants to read or write to the 24AA01/02(Figure 3-2).The 24AA01/02 monitors the bus for its correspondingslave address all the time. It generates an acknowledgebit if the slave address was true and it is not in a programmingmode.OperationFIGURE 3-2:ControlCodeChip SelectCONTROL BYTEALLOCATIONREAD/WRITER/WRead 1010 XXX 1Write 1010 XXX 0STARTX = Don’t careSLAVE ADDRESSR/W1 0 1 0 X X XA4.0 WRITE OPERATION4.1 Byte WriteFollowing the start signal from the master, the devicecode (4 bits), the don't care bits (3 bits), and the R/Wbit which is a logic low is placed onto the bus by themaster transmitter. This indicates to the addressedslave receiver that a byte with a word address will followafter it has generated an acknowledge bit during theninth clock cycle. Therefore the next byte transmitted bythe master is the word address and will be written intothe address pointer of the 24AA01/02. After receivinganother acknowledge signal from the 24AA01/02 themaster device will transmit the data word to be writteninto the addressed memory location. The 24AA01/02acknowledges again and the master generates a stopcondition. This initiates the internal write cycle, and duringthis time the 24AA01/02 will not generate acknowledgesignals (Figure 4-1).4.2 Page WriteThe write control byte, word address and the first databyte are transmitted to the 24AA01/02 in the same wayas in a byte write. But instead of generating a stop conditionthe master transmits up to eight data bytes to the24AA01/02 which are temporarily stored in the on-chippage buffer and will be written into the memory after themaster has transmitted a stop condition. After thereceipt of each word, the three lower order addresspointer bits are internally incremented by one. Thehigher order five bits of the word address remains constant.If the master should transmit more than eightwords prior to generating the stop condition, theaddress counter will roll over and the previouslyreceived data will be overwritten. As with the byte writeoperation, once the stop condition is received an internalwrite cycle will begin (Figure 7-1).Note:Page write operations are limited to writingbytes within a single physical page, regardlessof the number of bytes actually beingwritten. Physical page boundaries start ataddresses that are integer multiples of thepage buffer size (or Ôpage sizeÕ) and end ataddresses that are integer multiples of[page size - 1]. If a page write commandattempts to write across a physical pageboundary, the result is that the data wrapsaround to the beginning of the current page(overwriting data previously stored there),instead of being written to the next page asmight be expected. It is therefore necessaryfor the application software to preventpage write operations that would attempt tocross a page boundary.© 1998 Microchip Technology Inc. DS21052H-page 5

24AA01/02FIGURE 4-1:BUS ACTIVITYMASTERBYTE WRITESTARTCONTROLBYTEWORDADDRESSDATASTOPSDA LINESPBUS ACTIVITYACKACKACKFIGURE 4-2:BUS ACTIVITYMASTERSDA LINEBUS ACTIVITYPAGE WRITESTARTSCONTROLBYTEACKWORDADDRESS (n) DATA n DATA n + 1 DATA n + 7ACKACKACKACKSTOPPDS21052H-page 6© 1998 Microchip Technology Inc.

24AA01/025.0 ACKNOWLEDGE POLLINGSince the device will not acknowledge during a writecycle, this can be used to determine when the cycle iscomplete (this feature can be used to maximize busthroughput). Once the stop condition for a write commandhas been issued from the master, the device initiatesthe internally timed write cycle. ACK polling canbe initiated immediately. This involves the master sendinga start condition followed by the control byte for awrite command (R/W = 0). If the device is still busy withthe write cycle, then no ACK will be returned. If thecycle is complete, then the device will return the ACKand the master can then proceed with the next read orwrite command. See Figure 5-1 for flow diagram.FIGURE 5-1:ACKNOWLEDGE POLLINGFLOWSendWrite CommandSend StopCondition toInitiate Write CycleSend StartSend Control Bytewith R/W = 0Did DeviceAcknowledge(ACK = 0)?YesNextOperation6.0 WRITE PROTECTIONThe 24AA01/02 can be used as a serial ROM when theWP pin is connected to VCC. Programming will be inhibitedand the entire memory will be write-protected.No7.0 READ OPERATIONRead operations are initiated in the same way as writeoperations with the exception that the R/W bit of theslave address is set to one. There are three basic typesof read operations: current address read, randomread, and sequential read.7.1 Current Address ReadThe 24AA01/02 contains an address counter thatmaintains the address of the last word accessed, internallyincremented by one. Therefore, if the previousaccess (either a read or write operation) was toaddress n, the next current address read operationwould access data from address n + 1. Upon receipt ofthe slave address with R/W bit set to one, the 24AA01/02 issues an acknowledge and transmits the eight bitdata word. The master will not acknowledge the transferbut does generate a stop condition and the 24AA01/02 discontinues transmission (Figure 7-1).7.2 Random ReadRandom read operations allow the master to accessany memory location in a random manner. To performthis type of read operation, first the word address mustbe set. This is done by sending the word address to the24AA01/02 as part of a write operation. After the wordaddress is sent, the master generates a start conditionfollowing the acknowledge. This terminates the writeoperation, but not before the internal address pointer isset. Then the master issues the control byte again butwith the R/W bit set to a one. The 24AA01/02 will thenissue an acknowledge and transmits the eight bit dataword. The master will not acknowledge the transfer butdoes generate a stop condition and the 24AA01/02 discontinuestransmission (Figure 7-2).7.3 Sequential ReadSequential reads are initiated in the same way as a randomread except that after the 24AA01/02 transmits thefirst data byte, the master issues an acknowledge asopposed to a stop condition in a random read. Thisdirects the 24AA01/02 to transmit the next sequentiallyaddressed 8-bit word (Figure 7-3).To provide sequential reads the 24AA01/02 contains aninternal address pointer which is incremented by one atthe completion of each operation. This address pointerallows the entire memory contents to be serially readduring one operation.7.4 Noise ProtectionThe 24AA01/02 employs a VCC threshold detector circuitwhich disables the internal erase/write logic if theVCC is below 1.5 volts at nominal conditions.The SCL and SDA inputs have Schmitt trigger and filtercircuits which suppress noise spikes to assure properdevice operation even on a noisy bus.© 1998 Microchip Technology Inc. DS21052H-page 7

24AA01/02FIGURE 7-1:CURRENT ADDRESS READBUS ACTIVITYMASTERSTARTCONTROLBYTEDATA nSTOPSDA LINESPBUS ACTIVITYACKNOACKFIGURE 7-2:RANDOM READBUS ACTIVITYMASTERSDA LINEBUS ACTIVITYSTARTSCONTROLBYTEACKWORDADDRESS (n)ACKSTARTSCONTROLBYTEACKDATA (n)NOACKSTOPPFIGURE 7-3:SEQUENTIAL READBUS ACTIVITYMASTERCONTROLBYTEDATA n DATA n + 1 DATA n + 2 DATA n + XSTOPSDA LINEPBUS ACTIVITYACKACKACKACKNOACK8.0 PIN DESCRIPTIONS8.1 SDA Serial Address/Data Input/OutputThis is a bi-directional pin used to transfer addressesand data into and data out of the device. It is an opendrain terminal, therefore the SDA bus requires a pullupresistor to VCC (typical 10KΩ for 100 kHz, 2K for 400kHz).For normal data transfer SDA is allowed to change onlyduring SCL low. Changes during SCL high arereserved for indicating the START and STOP conditions.8.2 SCL Serial ClockThis input is used to synchronize the data transfer fromand to the device.8.3 WPThis pin must be connected to either VSS or VCC.If tied to VSS, normal memory operation is enabled(read/write the entire memory).If tied to VCC, WRITE operations are inhibited. Theentire memory will be write-protected. Read operationsare not affected.This feature allows the user to use the 24AA01/02 as aserial ROM when WP is enabled (tied to VCC).8.4 A0, A1, A2These pins are not used by the 24AA01/02. They maybe left floating or tied to either VSS or VCC.DS21052H-page 8© 1998 Microchip Technology Inc.

24AA01/02NOTES:© 1998 Microchip Technology Inc. DS21052H-page 9

24AA01/02NOTES:DS21052H-page 10© 1998 Microchip Technology Inc.

24AA01/0224AA01/02 PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office..24AA01/02 — /PPackage:TemperatureRange:P = Plastic DIP (300 mil Body), 8-leadSN = Plastic SOIC (150 mil Body), 8-leadSM = Plastic SOIC (207 mil Body), 8-leadBlank = 0°C to +70°CI = -40°C to +85°CDevice:24AA0124AA01T24AA0224AA02T1.8V, 1K I 2 C Serial EEPROM1.8V, 1K I 2 C Serial EEPROM (Tape and Reel)1.8V, 2K I 2 C Serial EEPROM1.8V, 2K I 2 C Serial EEPROM (Tape and Reel)Sales and SupportData SheetsProducts supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommendedworkarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:1. Your local Microchip sales office2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-72773. The Microchip Worldwide Site (www.microchip.com)Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.New Customer Notification SystemRegister on our web site (www.microchip.com/cn) to receive the most current information on our products.© 1998 Microchip Technology Inc. DS21052H-page 11

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