MAX192 Low-Power, 8-Channel, Serial 10-Bit ADC - Robotics UWA

t DSt DHLow-Power, 8-Channel,Serial 10-Bit ADCMAX192CSSCLKDIN1 4 8 12 16 20 24START SEL2 SEL1 SEL0UNI/BIPt AZRB1 RB2 RB3SSTRBRB2RB3DOUTA/D STATEIDLERB1SCL/DIFF PD1 PD0 B9ACQUISITIONAUTO ZERO1.5µs (CLK = 2MHz)RB2MSB B8 B7 B6 B5 B4 B3 B2 B1CONVERSIONRB3B0FILLED WITH LSB S1 SO ZEROSIDLEFigure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)CS• • •t CSHt CSSt CLt CSHSCLK• • •DIN• • •t DVt CHt DO t TRDOUT• • •Figure 7. Detailed Serial-Interface Timingthe MAX192 and three-states DOUT, but it does notadversely affect an internal clock-mode conversionalready in progress. When internal clock mode isselected, SSTRB does not go into a high-impedancestate when – C — S – goes high.Figure 10 shows the SSTRB timing in internal clockmode. In internal clock mode, data can be shifted inand out of the MAX192 at clock rates exceeding4.0MHz, provided that the minimum acquisition time,tAZ, is kept above 1.5µs.Data FramingThe falling edge of – C — S – does not start a conversion on theMAX192. The first logic high clocked into DIN is interpretedas a start bit and defines the first bit of the controlbyte. A conversion starts on the falling edge of SCLK,after the eighth bit of the control byte (the PD0 bit) isclocked into DIN. The start bit is defined as:The first high bit clocked into DIN with C –— S – low anytimethe converter is idle, e.g. after V DD is applied.ORThe first high bit clocked into DIN after bit 3 of aconversion in progress is clocked onto the DOUT pin.If a falling edge on – C — S – forces a start bit before bit 3(B3) becomes available, then the current conversionwill be terminated and a new one started. Thus, thefastest the MAX192 can run is 15 clocks per conversion.Figure 11a shows the serial-interface timing necessaryto perform a conversion every 15 SCLK cyclesin external clock mode.12 ______________________________________________________________________________________