MAX192 Low-Power, 8-Channel, Serial 10-Bit ADC - Robotics UWA

Low-Power, 8-Channel,Serial 10-Bit ADCMAX192Table 5.Worst-Case Power-Up Delay TimesReference Reference- VREF Power- Power-Up MaximumBuffer Buffer Capacitor Down Delay SamplingCompensation (µF) Mode (sec) Rate (ksps)ModeEnabled Internal Fast 5µ 26Enabled Internal Full 300µ 26Enabled External 4.7 Fast See Figure 14c 133Enabled External 4.7 Full See Figure 14c 133Disabled Fast 2µ 133Disabled Full 2µ 133Table 6. Software Shutdown and Clock ModePD1 PD0 Device Mode1 1 External Clock Mode1 0 Internal Clock Mode0 1 Fast Power-Down Mode0 0 Full Power-Down ModeIn external compensation mode, the power-up time is20ms with a 4.7µF compensation capacitor when thecapacitor is fully discharged. In fast power-down, youcan eliminate start-up time by using low-leakage capacitorsthat will not discharge more than 1/2LSB while shutdown. In shutdown, the capacitor has to supply the currentinto the reference (1.5µA typ) and the transient currentsat power-up.Figures 12a and 12b illustrate the various power-downsequences in both external and internal clock modes.Software Power-DownSoftware power-down is activated using bits PD1 andPD0 of the control byte. As shown in Table 6, PD1 andPD0 also specify the clock mode. When software shutdownis asserted, the ADC will continue to operate inthe last specified clock mode until the conversion iscomplete. Then the ADC powers down into a low quiescent-currentstate. In internal clock mode, the interfaceremains active and conversion results may beclocked out while the MAX192 has already entered asoftware power-down.The first logical 1 on DIN will be interpreted as a startbit, and powers up the MAX192. Following the start bit,the data input word or control byte also determinesTable 7. Hard-Wired Shutdown andCompensation ModeSHDN Device Reference-BufferState Mode Compensation1 Enabled Internal CompensationFloating Enabled External Compensation0 Full Power-Down N/Aclock and power-down modes. For example, if the DINword contains PD1 = 1, then the chip will remain poweredup. If PD1 = 0, a power-down will resume afterone conversion.Hardware Power-DownThe – S — H — D — N – pin places the converter into the fullpower-down mode. Unlike with the software shutdownmodes, conversion is not completed. It stops coincidentallywith – S — H D — N – being brought low. There is nopower-up delay if an external reference is used and isnot shut down. The S –— H D — N – pin also selects internal orexternal reference compensation (see Table 7).Power-Down SequencingThe MAX192 auto power-down modes can save considerablepower when operating at less than maximumsample rates. The following discussion illustrates thevarious power-down sequences.Lowest Power at up to 500Conversions/Channel/SecondThe following examples illustrate two differentpower-down sequences. Other combinations of clockrates, compensation modes, and power-down modesmay give lowest power consumption in other applications.16 ______________________________________________________________________________________