MAX192 Low-Power, 8-Channel, Serial 10-Bit ADC - Robotics UWA

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Low-Power, 8-Channel,Serial 10-Bit ADCsMAX192_____________________________________________________________Pin DescriptionPIN NAME FUNCTION1–8 CH0–CH7 Sampling Analog Inputs9, 13 AGNDAnalog Ground. Also IN- Input for single-enabled conversions. Connect both AGND pins toanalog ground.10 S — H D — N – rent, otherwise the MAX192 is fully operational. Pulling SHDN high puts the reference-buffer amplifierin internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in externalThree-Level Shutdown Input. Pulling SHDN low shuts the MAX192 down to 10µA (max) supply cur-compensation mode.11 VREFReference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier.Add a 4.7µF capacitor to ground when using external compensation mode. Also functions as aninput when used with a precision external reference.12 REFADJ Reference-Buffer Amplifier Input. To disable the reference-buffer amplifier, tie REFADJ to V DD.14 DGND Digital Ground15 DOUTSerial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when – C — S – ishigh.16 SSTRBSerial Strobe Output. In internal clock mode, SSTRB goes low when the MAX192 begins the A/Dconversion and goes high when the conversion is done. In external clock mode, SSTRB pulseshigh for one clock period before the MSB decision. SSTRB is high impedance when – C — S – is high(external mode).17 DIN Serial Data Input. Data is clocked in at the rising edge of SCLK.18 C — S – Active-Low Chip Select. Data will not be clocked into DIN unless – C — S – is low. When – C — S – is high,DOUT is high impedance.19 SCLKSerial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK alsosets the conversion speed. (Duty cycle must be 45% to 55%.)20 V DD Positive Supply Voltage, +5V ±5%+5V+5V3k3kDOUTDOUTDOUTDOUT3kC LOADC LOAD3kC LOADC LOADDGNDDGNDDGNDDGNDa. High-Z to V OH and V OL to V OH b. High-Z to V OL and V OH to V OL a V OH to High-Zb V OL to High-ZFigure 1. Load Circuits for Enable TimeFigure 2. Load Circuits for Disabled Time6 ________________________________________________________________________________________________
Low-Power, 8-Channel,Serial 10-Bit ADCCSSCLKDINSHDN18191710CH01CH1 2CH2 3CH3 4CH4 5CH5 6CH6 7 CH7 8AGND 13AGND 9REFADJ12VREF 11INPUTSHIFTREGISTERANALOGINPUTMUX+2.46VREFERENCECONTROLLOGICT/HINTCLOCKA ≈ 1.6520kCLOCKINSARADCOUTREF+4.096VOUTPUTSHIFTREGISTERMAX19215162014DOUTSSTRBV DDDGNDCH0CH1CH2CH3CH4CH5CH6CH7AGNDVREFINPUTMUXCAPACITIVE DACC HOLD– +16pFC SWITCHTRACKT/HSWITCHZERO10kR SHOLDCOMPARATORAT THE SAMPLING INSTANT,THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.SINGLE-ENDED MODE: IN+ = CHO-CH7, IN- = AGND.DIFFERENTIAL MODE (BIPOLAR): IN+ AND IN- SELECTED FROM PAIRS OFCH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.MAX192Figure 3.Block Diagram_______________Detailed DescriptionThe MAX192 uses a successive-approximation conversiontechnique and input track/hold (T/H) circuitry toconvert an analog signal to a 10-bit digital output. Aflexible serial interface provides easy interface tomicroprocessors. No external hold capacitors arerequired. Figure 3 shows the block diagram for theMAX192.Pseudo-Differential InputThe sampling architecture of the ADC’s analog comparatoris illustrated in the Equivalent Input Circuit(Figure 4). In single-ended mode, IN+ is internallyswitched to CH0–CH7 and IN- is switched to AGND. Indifferential mode, IN+ and IN- are selected from pairsof CH0/CH1, CH2/CH3, CH4/CH5 and CH6/CH7. Referto Tables 1 and 2 to configure the channels.In differential mode, IN- and IN+ are internally switchedto either one of the analog inputs. This configuration ispseudo-differential to the effect that only the signal atIN+ is sampled. The return side (IN-) must remain stablewithin ±0.5LSB (±0.1LSB for best results) withFigure 4. Equivalent Input Circuitrespect to AGND during a conversion. Accomplish thisby connecting a 0.1µF capacitor from AIN- (the selectedanalog input, respectively) to AGND.During the acquisition interval, the channel selected asthe positive input (IN+) charges capacitor C HOLD . Theacquisition interval spans three SCLK cycles and endson the falling SCLK edge after the last bit of the inputcontrol word has been entered. At the end of the acquisitioninterval, the T/H switch opens, retaining chargeon CHOLD as a sample of the signal at IN+.The conversion interval begins with the input multiplexerswitching CHOLD from the positive input (IN+) to thenegative input (IN-). In single-ended mode, IN- issimply AGND. This unbalances node ZERO at the inputof the comparator. The capacitive DAC adjusts duringthe remainder of the conversion cycle to restore itsnode ZERO to 0V within the limits of its resolution. Thisaction is equivalent to transferring a charge of16pF x (VIN+ - VIN-) from CHOLD to the binary-weightedcapacitive DAC, which in turn forms a digital representationof the analog input signal._______________________________________________________________________________________ 7
Page 1: 19-0247; Rev. 0; 3/94______________
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MAX192 Low-Power, 8-Channel, Serial 10-Bit ADC - Robotics UWA

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