An Operating Systems Vade Mecum

88 Space Management Chapter 3first splits the virtual address into two parts: the page number and the offset. Here ishow a typical translation table might look:1 type2 AccessType = (Read, Write, Execute);3 PageTableEntry =4 record5 Location : PageFrameNumber;6 Permissions : set of AccessType;7 Present : Boolean;8 end;9 var10 PageTable: array 0 : PageLimit-1 of PageTableEntry;11 NumberOfPages : 0 .. PageLimit;Because pages are aligned to page frames in physical store, the table need not keep physicaladdresses for the Location field; the page frame number suffices. Here is the algorithmfollowed by the hardware to translate each access:12 procedure Translate (VA : VirtualAddress; AT : AccessType) : PhysicalAddress;13 var14 VirtualPage : 0 .. PageLimit − 1;15 Offset : 0 .. PageSize − 1;16 begin17 VirtualPage := VA div PageSize; { performed by extracting bits }18 Offset := VA mod PageSize; { performed by extracting bits }19 if VirtualPage ≥ NumberOfPages then20 trap("invalid page number");21 else22 with PageTable[VirtualPage] do23 if not Present then24 trap("missing page"); { page fault; not an error }25 elsif not AT in Permissions then26 trap("security violation");27 else28 Translate := Location*PageSize + Offset;29 end; { if }30 end; { with }31 end; { if }32 end Translate;Figure 3.13 shows the algorithm followed by the hardware on every access totranslate and check addresses. This algorithm involves checking the page table, which istypically in main store, for every translation. (Some early machines, such as the Nova3/D, stored page tables in high-speed registers, but this design has become less popularwith potentially large page tables.) To reduce the time required for translation, manymachines provide a translation look-aside buffer (TLB) to hold the most frequentlyused parts of the current page table. The hardware simultaneously tries to find thedesired entry in the TLB and in main store. If the entry is in the TLB (there is a cachehit), the hardware finds it very quickly (on the order of 100 nanoseconds) and aborts itsattempt to get the entry from main store, an operation that would have taken about onemicrosecond to complete. If the entry is not in the TLB (there is a cache miss), themain-store reference is allowed to complete, and its value is not only used for addresstranslation but also placed in the TLB for future use. We will postpone discussing whichentry in the TLB is discarded in this case; the policies are very similar to policies we willintroduce for page replacement. Typical translation look-aside buffers can achieve a 95percent hit ratio.