An Operating Systems Vade Mecum

158 Transput Chapter 5processeskerneldevice driverdevice interfacestatusdeviceorderscontrollerdevicedatadeviceinterrupts2.2 Direct memory access (DMA)Figure 5.5 Devices connected by a controllerUsing device registers to transfer data places a heavy burden on the cpu, which must servicean interrupt after every word has been transferred to or from the device. This burdenis especially severe for devices that transfer information so rapidly that the cpu couldnot keep the device busy because it could not service interrupts fast enough. However,some of these devices cannot wait very long for the next word of data. A writing tapedrive or a disk drive that is not sent data quickly enough is likely to write garbage on thetape or disk. Polling, especially busy waiting, would keep up with the device at the costof preventing any other computation from taking place.Direct memory access (DMA) is a hardware technique designed to relieve the cpuof this burden for fast devices. DMA is demonstrated in Figure 5.6. Data are nottransferred through device registers but are placed in or retrieved from main storedirectly by the device. The cpu can transmit instructions or orders to the device or controllerthrough registers, as before, but the instructions include information describingwhere the data should be placed or found in main store. Physical store is usually usedbecause the DMA hardware is not attached to address-translation hardware. Interruptsare used to signal the end of an entire transfer, which could transmit thousands of wordsbetween the cpu and the device. During the course of the transfer, the status of the deviceis available to the cpu if it should want to find out how it is going.For fast devices like disks, there is a chance that main store cannot keep up withthe device, especially if there are several DMA transfers taking place at once. If mainstore cannot supply the next byte to write to the disk when it is needed, the transfer terminateswith an overrun error. Likewise, overrun can occur if main store cannot savedata being read from the disk before the next data are available. Overruns are preventedby disk controllers that perform some internal data buffering. Some disk controllers havea cache that can hold a track of data. These controllers can read entire tracks from thedisk at one time and store the data in the cache until the computer asks for them.