Switch Mode Power Supply (SMPS) Topologies (Part II) - Microchip

AN1207Switch Mode Power Supply (SMPS) Topologies (Part II)Author:INTRODUCTIONThis application note is the second of a two-part serieson Switch Mode Power Supply (SMPS) topologies.The first application note in this series, AN1114 -“Switch Mode Power Supply (SMPS) Topologies (PartI)”, explains the basics of different SMPS topologies,while guiding the reader in selecting an appropriatetopology for a given application.Part II of this series expands on the previous materialin Part I, and presents the basic tools needed to designa power converter. All of the topologies introduced inPart I are covered, and after a brief overview of thebasic functionality of each, equations to design realsystems are presented and analyzed. Beforecontinuing, it is recommended that you read andbecome familiar with Part I of this series.CONTENTSAntonio BersaniMicrochip Technology Inc.This application note contains the following majorsections:Requirements and Rules............................................ 1Buck Converter .......................................................... 2Boost Converter ....................................................... 14Forward Converter ................................................... 18Two-Switch Forward Converter................................ 30Half-Bridge Converter .............................................. 39Push-Pull Converter................................................. 47Full-Bridge Converter............................................... 57Flyback Converter.................................................... 66Voltage and Current Topologies............................... 76Conclusion ............................................................. 104References............................................................. 104Source Code .......................................................... 105REQUIREMENTS AND RULESThe following requirements and rules were used todetermine the various component values used in thedesign of a power converter.The general design requirements are listed as follows:• Nominal input voltage (VDC)• Minimum input voltage (VDC, min)• Maximum input voltage (VDC, max)• Output voltage (VOUT)• Nominal average output current (IO, av, nom)• Nominal minimum output current (IO, av, min)• Maximum ripple voltage (VR, max)In addition, a few common rules were used forcomponent selection:• MOSFETs (or switches) must be able to:- Withstand the maximum voltage- Withstand the maximum current- Operate efficiently and correctly at the frequencyof the PWM- Operate in the SOA (dependant on dissipation)• Diodes must be able to:- Withstand the maximum reverse voltage- Withstand the average currentArrows are used in the circuit schematics to representvoltages. The voltage polarity is not directly reflected bythe arrow itself (meaning if the voltage reverses, thearrow is not reversed, but that the value of the voltageis negative).© 2009 Microchip Technology Inc. DS01207B-page 1

AN1207BUCK CONVERTERThe Buck Converter converts a high input voltage intoa lower output voltage. It is preferred over linearregulators for its higher efficiency.Topology EquationsFigure 1 shows the basic topology of a Buck Converter.The Q1 switch is operated with a fixed frequency andvariable duty cycle signal.FIGURE 2:VDCQ1BUCK CONVERTERTOPOLOGY: TON PERIODD1LOVLCOVOUTFIGURE 1:VDCQ1BUCK CONVERTERTOPOLOGYAccordingly, voltage VI is a square-wave s(t). TheFourier series of such a signal is shown in Equation 1.EQUATION 1:This means that the square-wave can be representedas a sum of a DC value and a number of sine waves atdifferent, increasing (multiple) frequencies. If this signalis processed through a low-pass filter (Equation 2), theresulting output (DC value only) is received.EQUATION 2:VID1A LoCo low-pass filter extracts from the square-waveits DC value and attenuates the fundamental andharmonics to a desired level.Q1 CLOSED (TON PERIOD)In this configuration, the circuit is redrawn as shown inFigure 2. The diode is reverse-biased so that itbecomes an open circuit.LOVLst () = A-- τ + ΣsinTCOVOUTwaves_with_frequency_multiple_of_the_square_wave_frequencywhere:τ = the duty cycleT = the periodA = the square-wave amplitudes f() t = A-- τ = constTBased on Figure 2, the voltage on the inductor is asshown in Equation 3.EQUATION 3:V L= V DC– V Qon ,– V OUTThe inductor current (having a constant time derivativevalue) is a ramp:( V DC– V Q, on– V OUT)i L() t = i L( 0)+ -------------------------------------------------------tL OAt time TON, equals:( V DC– V Qon ,– V OUT)i L( T ON) = i L( 0)+ -------------------------------------------------------T ONWhere T ON is the duration of the time interval when theswitch Q1 is closed.Q1 OPEN (TOFF PERIOD)As shown in Figure 3, when the switch Q1 opens, theinductor will try to keep the current flowing as before.FIGURE 3:VDCQ1BUCK CONVERTERTOPOLOGY: TOFF PERIODD1As a result, the voltage at the D1, LO, Q1 intersectionwill abruptly try to become very negative to support thecontinuous flow of current in the same direction (seeFigure 4).LOVLL OCOVOUTDS01207B-page 2© 2009 Microchip Technology Inc.

AN1207FIGURE 4:VLINDUCTOR BEHAVIORILDuring TON, the inductor isstoring energy into itsmagnetic field (VL > 0).INPUT/OUTPUT RELATIONSHIP AND DUTYCYCLEWhat has been described until now is called Continuousmode. To understand what it is and its importance,refer to Figure 5(G), which represents the inductor current.As previously seen, there is a ramp-up during TONand a ramp-down during TOFF.The average current can be computed easily usingEquation 6.VLDuring TOFF, the inductor isreleasing energy previouslystored (VL < 0).EQUATION 6:I 2+ I 1,= --------------2I LavEquation 4 shows the resulting inductor voltage, whileEquation 5 shows the current.EQUATION 4:ILV L= – V OUT– V Don ,The average inductor current is also the current flowingto the output, so the output average current is equal toEquation 7.EQUATION 7:I 2+ I 1,= --------------2I OavEQUATION 5:– V OUT– V Don ,i L() t = i L( T ON) + ------------------------------------- tL O© 2009 Microchip Technology Inc. DS01207B-page 3

AN1207FIGURE 5:BUCK CONVERTER WAVEFORMSQ1 Commandt(A)VDC + VD, onVQ1t(B)I2I1IQ1t(C)VD1t(D)(-VDC + VQ, on)I2I1ID1t(E)VDC - VOUTVLAt(F)B-VOUTI2I1ILt(G)TONTOFFT(A) = Command signal and MOSFET gate(B) = Voltage and MOSFET(C) = Current flowing into MOSFET(D) = Voltage on D1 diode(E) = Current in D1 diode(F) = Voltage on LO inductor(G) = Current in LO inductorDS01207B-page 4© 2009 Microchip Technology Inc.

AN1207Supposing the output load RO (connected in parallel tothe output capacitor CO) changes by increasing, thischange has the effect of reducing the average outputcurrent. As shown in Figure 6, current moves from lineA for the nominal load, to line B for a larger load. Whatshould be noted is that the slopes of the two ramps,both during TON and TOFF, do not change because,they only depend on VDC, VOUT and L, and they havenot been changed. As a consequence, increasing theload results in RO becoming greater. Since VO equalsconstant (the control loop explained earlier handlesthis) and RO increases, the current diminishes.FIGURE 6:VLINDUCTOR CURRENT AT DIFFERENT LOADSTTONTOFFIncreasing load(reducing IO, av)ABCDCONTINUOUS MODEOperating in the Continuous mode is so named sincethe current in the inductor never stops flowing (goes tozero).As shown in Figure 6, if the load continues to increase(reducing IO, av), at some time the inductor current plotwill touch the x-axis (line C). This means the initial andfinal current (at the beginning and the end of the switchingperiod) in the inductor is zero. At this point, theinductor current enters what is considered as Criticalmode.If the load is further increased, the current during thedown-ramp will reach zero before the end of the periodT (line D), which is known as Discontinuous mode.Note:In Discontinuous mode, the only way tofurther decrease the inductor current is toreduce the ON time (TON).One key point is that the inductor current at the end ofthe TOFF period must equal the inductor current at thebeginning of the TON period, meaning the net change incurrent in one period must be zero. This must be trueat Steady state, when all transients have finished, andthe circuit behavior is no longer changing.TONUsing the value of IL(TON) derived from Equation 3 andEquation 5 creates the relationship shown inEquation 8.EQUATION 8:ΔI LV DC– V Qon ,– V OUT∝ ( )T =( ONV OUT+ V )T D,on OFFNeglecting VD, on and VQ, on, Equation 8 can besolved for VOUT, as shown in Equation 9.EQUATION 9:V OUT= V DCDwhere D = Ton / T (duty cycle), orV OUTD = -------------V DCThe maximum duty cycle is achieved when the inputvoltage is at its minimum, as shown in Equation 10.EQUATION 10:D max=V-------------------- OUTV DC,mintTherefore, D must obviously be between ‘0’ and ‘1’.© 2009 Microchip Technology Inc. DS01207B-page 5

AN1207FIGURE 8:DUTY CYCLE IN CONTINUOUS AND DISCONTINUOUS REGIONSD1VDC/VOUT = 1.25(A)VDC/VOUT = 2Discontinuous regionContinuous regionVDC/VOUT = 5.01IO/IO, limitAs shown in Figure 8, starting from the continuousregion and moving along line (A), where D = 0.5, assoon the boundary between continuous anddiscontinuous regions (dotted line) is crossed, to keepthe same output voltage (VDC/VOUT = 2), D changesaccording to the nonlinear relation in Equation 12.Design Equations and ComponentSelectionThis section determines the equations that enable thedesign of a Continuous mode Buck Converter.INDUCTORThe average minimum current (IO, av, min) is set as theaverage output current at the boundary of Discontinuousmode (Figure 7). This way, for any current largerthan IO, av, min, the system will operate in Continuousmode. Usually it is a percentage of IO, av, nom, wherea common value is 10%, as shown in Equation 13.EQUATION 13:1 ( V DC, nom– V OOUT)= ,= 0.1I o, av,nom= --I2 2= ------------------------------------------------- T2L ONOI o, av,minI O limitSolving Equation 13 with respect to LO results inEquation 14.EQUATION 14:L O5 ( V DC, nom– V )V OUT= --------------------------------------------------------------- OUTV DC, nomF PWMI O,av,nomwhere FPWM is the PWM frequency (FPWM =1/T)Power Losses In The InductorPower losses in the inductor are represented byEquation 15.EQUATION 15:P LOSS, inductor= I O,av,nom( ) 2 ESRwhere ESR is the equivalent inductor resistance© 2009 Microchip Technology Inc. DS01207B-page 7

AN1207OUTPUT CAPACITORThe current ripple generates an output voltage ripplehaving two components, as shown in Figure 9.Power Losses in the CapacitorPower losses dissipated in the capacitor are shown inEquation 19.FIGURE 9:MODEL OF THE OUTPUTCAPACITOR COCORESR (ESR)LESL (ESL)EQUATION 19:DIODEReferring to Figure 5(E), the current flowing throughthe diode during TOFF is the inductor current. It is easythen to compute the average diode current usingEquation 20.EQUATION 20:2P LOSS, capacitor= ΔI LR ESRThe first component of the ripple voltage (VR) is causedby the effect series resistance (ESR) of the outputcapacitor. This resistance is shown in Figure 9 asRESR.The second component, VR,CO, comes from thevoltage drop caused by the current flowing through thecapacitor, which results in Equation 16.EQUATION 16:V R ESRThe two contributions are not in phase; however, consideringthe worst case, if they are summed in phase,this results in one switching period, as shown inEquation 17.EQUATION 17:,= R ESR( I 2– I 1) = R ESRΔI Lwhere (I 2 - I 1 ) is the ripple current flowing in the inductorand to the output (at the edge of Discontinuous mode,which is: ΔI L = 2 I O , limit), andV R CO ,=1= ------ iC OC∫()dt tΔV R,totalR ESRΔI L------1 D+ ΔI L--------------C OF PWMThe maximum reverse voltage the diode has to withstandis during TON (see Figure 5(D)), as shown inEquation 21.EQUATION 21:Power Dissipation Computation in the DiodeBecause voltage on the diode is non-zero (VR), but thecurrent is zero, dissipation during TON is equal toEquation 22.EQUATION 22:Dissipation during TOFF is equal to Equation 23.EQUATION 23:P D TOFFI D, av= I O av,nom,( 1 – D)V R, max= – V DC, max+ V Q,onP D , TON= 0,= V fI O av,nom------------ = VT fI O, av,nom( 1 – D),T OFFBy rearranging terms, the required capacitor valueneeded to guarantee the specified output voltage rippleis shown in Equation 18.EQUATION 18:C OΔI LDV R,total= ---------------------------------------------------------------------F PWM[ Δ – R ESRΔI L]MOSFETThe maximum voltage on the switch (see Figure 5(B))during TOFF is shown in Equation 24.EQUATION 24:V Q, max= V DC, max+ V D,onDS01207B-page 8© 2009 Microchip Technology Inc.

AN1207The required inductor with the minimum input voltage isshown in Equation 38.EQUATION 38:An inductor of at least 42 µH will prevent the converterfrom going discontinuous over the full input voltagerange.In fact, if the smallest inductor, L = 26 µH is selected,the maximum input voltage (VDC = 15.5V) would resultin a current ripple of I2 - I1 = 0.85A. Conversely, theinductor L = 42 µH with an input voltage of 8.5V givesa current ripple of 0.17A. This means that any inductorgreater than 42 µH will fit.Output CapacitanceEquation 39 is supposing to select a capacitancehaving ESR = 30 mΩ.EQUATION 39:V DC– V OUT,------------------------------ V OUT 1------------- --------------8.5---------------– 5------5 1== ⋅ ⋅ ------------ = 26μH0.2 ⋅ 2 8.5 200KL O m0.2I O,av,nomV DCF PWMCΔI LD--------------------------------------------------------------------0.4 ⋅ 0.42= = -------------------------------------------------------------------------------F PWM[ V RIPPLE– R ESRΔI L]200K[ 50 ⋅ 10 – 3 – 30 ⋅ 10 – 3 = 22μF⋅ 0.4 ]Input CapacitorUsing the same approach to compute the outputcapacitance, the input capacitance is then calculatedusing Equation 40.EQUATION 40:CΔI LD--------------------------------------------------------------------0.4 ⋅ 0.42= = --------------------------------------------------------------F PWM[ V RIPPLE– R ESRΔI L]200K[ 0.2 – 30 ⋅10 3 = 4.5μF⋅ 0.4]Free-Wheeling Diode SelectionBased on Equation 21 (see also Figure 5(D)), the maximumreverse voltage on the diode during TON is thencalculated, as shown in Equation 41.EQUATION 41:V R, max= – V DC, max+ V Q on,≈ – 15.5VAccording to Equation 20, the average current in thediode is calculated, as shown in Equation 42.EQUATION 42:I D, av= I O av,nom,( 1 – D) = 2 ⋅ ( 1 – 0.42) = 1.16ADS01207B-page 12© 2009 Microchip Technology Inc.

AN1207MOSFET selectionThe key parameters for the selection of the MOSFET arethe average current and the maximum voltage (referringto Equation 24 and Equation 25). The resultingcalculations are shown in Equation 43 and Equation 44.EQUATION 43:V Q, max= V DC max,+ V D≈ 15.5VEQUATION 44:I Q, av= I O av,nom,D = 2 ⋅ 0.42 = 0.84AThe power dissipated in the MOSFET can be computedwith Equation 35, which results in Equation 45,where typical values of VF = 1V and Tsw = 100 ns areused.EQUATION 45:P LOSS maxT SW,DV fI O, av,nom2V DCI O, av,nom---------100ns=+= 0.42 ⋅1V ⋅2A + 2 ⋅15.5V ⋅2A⋅ -------------- = 0.84 + 1.24 = 2.08WT5μs© 2009 Microchip Technology Inc. DS01207B-page 13

AN1207BOOST CONVERTERA Boost Converter converts a lower input voltage to ahigher output voltage.Topology EquationsFigure 11 shows the essential topology of a BoostConverter.Q1 OPEN (TOFF PERIOD)When the switch opens (Figure 13), and since theinductor current cannot change abruptly, the voltagemust change polarity. Current then begins flowingthrough the diode, which becomes forward-biased.FIGURE 13:BOOST CONVERTERTOPOLOGY: TOFF PERIODFIGURE 11:VLL1VDCBOOST CONVERTERTOPOLOGYQ1D1VOUTCOROVOUTVLVDL1D1VOUTVDCQ1CO ROThe resulting inductor voltage is shown in Equation 48.EQUATION 48:Q1 CLOSED (TON PERIOD)In this configuration, the circuit is redrawn as shown inFigure 12.FIGURE 12:VDCVLL1BOOST CONVERTERTOPOLOGY: TON PERIODThe resulting voltage on the inductor is shown inEquation 46.EQUATION 46:Based on the inductor equation (Equation 46) thecurrent results are shown in Equation 47.EQUATION 47:Q1D1V L= V DC– V Q,onVOUTCO( V DC– V Q,on)I L() t = I L( 0)+ -----------------------------------tL 1ROVOUTThe current flowing into the inductor during TOFF, whichis ramping down, is computed using Equation 49.EQUATION 49:V L= V DC– V D, on– V OUT< 0– V D, on– V OUTI L() t = IT ( ON) + --------------------------------------------------tOPERATING MODESV DCLike the Buck Converter, the Boost Converter can alsobe operated in Continuous and Discontinuous modes.The difference between the two modes is in the inductorcurrent. In Continuous mode it never goes to zero,whereas in Discontinuous mode, the falling inductorcurrent in the TOFF period reaches zero before the startof the following PWM period.As in the case of the Buck Converter, the Boost Convertercan be used in both modes. In either case, thecontrol loop must be considered. A solution for onemode does not necessarily work well with the other.Continuous Operating ModeAs usual, the two areas below the inductor voltageduring TON and TOFF must be equal. This means thatthe current at the beginning of the PWM period equalsthe current at the end (Steady state condition) of thePWM period. Using Equation 47 and Equation 49, therelation shown in Equation 50 can be made.L 1DS01207B-page 14© 2009 Microchip Technology Inc.

AN1207EQUATION 50:V OUTwhere D is the duty cycle of the PWM signal.=V DC------------1 – DIt is important to note that this is a nonlinear relationship(Figure 14), unlike the Buck transfer function.If a lossless circuit is assumed, PO =PDC, VOIO =VDCIDC, resulting in Equation 51.EQUATION 52:The power delivered to the load by the input duringTOFF is shown in Equation 53.EQUATION 53:P Lwhere Ip is the inductor peak current=L 1I 2 P-------------2TEQUATION 51:P DC=I PT FV DC-----------2TI O-------- = ( 1 – D)I DCDiscontinuous Operating ModeTo find the I/O relationship, a different approach is usedwhere energy is considered, which differs from theapproach used for Buck Converters.The total power (PT) delivered to the load comes fromthe contribution of the magnetic field in the inductorand, during TOFF, from the input voltage VDC.The power delivered from the inductor (assuming100% efficiency) is shown in Equation 52.where TF, as indicated in Figure 15(G), is the portion of theTOFF period from TON to when the inductor current reacheszero.The total power delivered to the load is the sum ofEquation 52 and Equation 53. The peak current isderived from Equation 47. If TON + TF = kT, the resultsare that of Equation 54.EQUATION 54:kRV OUTV OT=ONDC--------------------2L 1where RO is the output load resistorFIGURE 14:VO/VDC1201008060Series1402001 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93 97D%© 2009 Microchip Technology Inc. DS01207B-page 15

AN1207FIGURE 15:BOOST CONVERTER WAVEFORMS (DISCONTINUOUS MODE)TONTOFFQ1 CommandVD + VOUTt(A)VQ1t(B)IQ1t(C)VD1(A)t(D)-VOUT + VQID1t(E)VDCVLt(F)(B)VDC - VOUTILt(G)TF(A) = Command signal on Q1 MOSFET gate(B) = Voltage on Q1 MOSFET(C) = Current flowing into Q1 MOSFET(D) = Voltage on D1 diode(E) = Current in D1 diode(F) = Voltage on LO inductor(G) = Current in LO inductorDS01207B-page 16© 2009 Microchip Technology Inc.

AN1207Q1 ON (INTERVAL 0 - TON)For this configuration, the circuit is redrawn as shownin Figure 18.FIGURE 18:FORWARD CONVERTER TOPOLOGY: INTERVAL 0 - TOND1V RNRVAAD2BV BLONPNSV SD3VLCOROVOUTVDCVPQ1Input Circuit BehaviorThe input voltage is directly connected to the windingNP, and consequently, the dot end of this winding ispositive respect to the non-dot end. Similarly the dotend of NR has a higher voltage than the non-dot end.Diode D1 is reverse-biased and no current flows intothe winding NR. The voltage on the winding NP isshown in Equation 65.EQUATION 65:The voltage on winding NR is shown in Equation 66.EQUATION 66:V RV P onN RN P,= V DC– V Q,on= ------V P on= ------ ( V DC– V Q,on)N R,N PThe magnetizing current flowing into the NP windingsand the switch Q1 circuit (current that would be flowinginto the transformer if the secondary winding wereopen), is equal to Equation 67.The total current flowing into NP is the sum of the magnetizingcurrent and the output current reflected to theprimary through the transformer.Output Circuit BehaviorBecause of the voltage polarity on the primarywindings, the dot end of the secondary winding ispositive compared to its non-dot end. Consequently,D2 is forward-biased, while D3 is reverse-biased.The secondary winding voltage is shown inEquation 69.EQUATION 69:V SThe voltage to the right of the rectifying diode D2 isshown in Equation 70.EQUATION 70:N SN P= ------ ( V DC– V Q,on)V B= V S– V D on= ------ ( V DC– V ) V Q,on– D , onN S,N PEQUATION 67:I M() tV P= ------t =L MV DC– V Q,onL M------------------------------tThe voltage on the output inductor is shown inEquation 71.EQUATION 71:A positive-slope ramp whose maximum value isreached at TON is shown in Equation 68.V LN S= ------ ( V DC– V ) V Q,on– – D onN P,V OUTEQUATION 68:I M( T ON)=V DC– V Q,onL M------------------------------T ONThe current flowing through the output inductor andthrough D2 is shown in Equation 72.© 2009 Microchip Technology Inc. DS01207B-page 19

AN1207EQUATION 72:------ ( VN DC– V Q,on)– V D, on– V OUTPI L() t = I L( 0)+ ---------------------------------------------------------------------------------tAt this point, the total current flowing into the primarycan be computed. It has two contributions: the magnetizingcurrent (see Equation 67) and the load currentreflected back into the primary, as shown inEquation 73.EQUATION 73:N SI P totalL O------ ( VV DC– V Q,onN SN DC– V Q,on)– V D, on– V OUT,I L( 0)------------------------------t ------ P= + + ---------------------------------------------------------------------------------tL MN PN SL OQ1 OFF [INTERVAL TON - (TON + TR)]Based on this configuration, the circuit is redrawn, asshown in Figure 19.FIGURE 19:FORWARD CONVERTER TOPOLOGY: INTERVAL TON - (TON + TR)D1VRNRVAAD2BVBLONPNSVSD3VLCOROVOUTVDCVPQ1DS01207B-page 20© 2009 Microchip Technology Inc.

AN1207Input Circuit BehaviorBefore the switch Q1 was opened, the magnetizingcurrent was flowing in NP. When the switch opens, itreverses all the voltages to continue the flow. The dotend of NR becomes negative in respect to the non-dotend, and a similar behavior is experienced by thewinding NP. Because of the polarity on NR, diode D1becomes forward-biased and keeps the voltage at thedot end of NR, one diode drop below ground.Magnetizing current can now flow through NR anddiode D1 into the power supply VDC, as shown inFigure 19. The voltage VR on NR is shown inEquation 74.EQUATION 74:The voltage on NP is shown in Equation 75.EQUATION 75:When t = TON, the current in the reset winding equalsthe magnetizing current IM multiplied by the windingsration, as shown in Equation 76.EQUATION 76:V R= –( V DC+ V D,on) < 0N PV P, off= ------N R– ( V DC+ V D,on) < 0Output Circuit BehaviorAs previously mentioned, the magnetizing currentreverses all voltages when the switch Q1 turns off. Asa result, the dot end of the secondary winding is morenegative than the non-dot end and diode D2 becomesreverse-biased.The secondary voltage is shown in Equation 77.EQUATION 77:To keep the current flowing into inductor LO, its voltagereverses so that the left end of the inductor is more negativethan the right end, and it would continuouslydecrease; however, the freewheeling diode D3,becoming forward-biased and sets VB to a diode voltagedrop below ground. The voltage on the inductor isnow equal to Equation 78.EQUATION 78:Consequently the inductor current will decreaseaccording to Equation 79:EQUATION 79:N SV S, off= ------N RV L– ( V DC+ V D,on)= – V OUT– V D,onI R=N PN R------I MV OUT+ V D,onI L() t = IT ( ON) – ---------------------------------- tL ODuring TR, this current has a down-slope and reacheszero when t = TON + TR.This current is the same current that is flowing into thefree-wheeling diode D3.© 2009 Microchip Technology Inc. DS01207B-page 21

AN1207Q1 OFF [INTERVAL (TON + T R ) TO T]In this configuration, the circuit is redrawn as shown inFigure 20.FIGURE 20:FORWARD CONVERTER TOPOLOGY: INTERVAL (TON + TR) - TD1VRNRVAAD2BVBLONPNSVSD3VLCOROVOUTVDCVPQ1Input Circuit BehaviorAs soon as the magnetizing current reaches zero (atTON + TR), all of the energy that had been stored intothe transformer when TON has been released anddiode D1 opens. Consequently, the voltage drop on NRbecomes zero and the voltages at both the dot end andthe non-dot end of NR equal VDC. The voltage drop onNP equally becomes zero, so that now the voltageapplied to the switch is VDC.Output Circuit BehaviorNothing changes compared to the previous timeinterval.Design Equations and ComponentSelectionINPUT/OUTPUT RELATIONSHIP AND DUTYCYCLEAt the output, at steady state, the current in the inductorLO at t = 0, must equal the current at t = T. Expressingthe inductor voltage as a function of the inductor currentbased on Equation 72 and Equation 78, results inEquation 80, which in turn solves Equation 81.EQUATION 80:N S------ ( VN DC– V Q,on)– V D, on– V OUT------------------------------------------------------------------------------ PT ON==L OV OUT+ V D,onL O---------------------------------- T OFFEQUATION 81:V OUTThe magnetizing current, at time t = 0 and t = TON + TRis zero (at Steady state). Therefore, ΔIM during TONmust equal ΔIM during TR, which is represented byEquation 82 (refer to Equation 65 and Equation 75).EQUATION 82:V DCL MThe circuit is now running at the maximum duty cyclewhen TR equals TOFF, which means the full TOFF periodis needed to nullify the magnetizing current. In thiscase, in Equation 82, TR is replaced with its maximumtheoretical value TOFF, so that TON, max, as shown inEquation 83, is derived from Equation 84.EQUATION 83:EQUATION 84:N S= ------ ( V DC– V )D V Q,on– D , onN PN RL MN PN--------- PT ON------ V DC= --------- T R⇒ T ON= ------T RN PT ON, max=N R------T OFF⇒N PT ON, max=N R1D max, theoretical= ---------------N R1 + ------N PN R------ ( T – T ON,max)In the case of NR = NP, Dmax, theoretical = 0.5.DS01207B-page 22© 2009 Microchip Technology Inc.

AN1207TRANSFORMER: PRIMARYThe core of the transformer during operation moves inthe first quadrant of the hysteresis curve.The change in flux, according to the Faraday law, asshown in Equation 85, is proportional to the product ofthe applied voltage VP, and the time Tx, during whichthis voltage is present.EQUATION 85:In general, TON + TR = kT; the maximum value for TONis chosen as TON, max = kT/2 when NP = NR. As indicatedin Figure 21, the maximum value of TON is alsodependent on the ration NP/NR. Based on the characteristicsof the transformer core, ΔB is defined. FromEquation 85, the primary number of turns can be determined,considering the minimum value of VDC and consequently,the maximum duty cycle as shown inEquation 86.V P⋅ T XEQUATION 86:ΔB = -------------------N PA coreD maxN P=where the units are Tesla for ΔB and m 2 for AF ----------------------------------- (core PWMA coreΔBV DC ,– V min Q,on)During TON, this product equals (VDCTON), while duringTR the product is NPVDC(TR)/NR, based on Equation 65and Equation 75, neglecting VQ, on and VD, on.In Figure 22(F), the product (VDCTON) equals area A1,while VDCNPTR/NR equals area A2.It is preferable to have a net ΔB = 0, so that in thehysteresis plane, the operating point at the end of thePWM period has come back to the initial point. Thisguarantees that the system will never drift towardsaturation.The point is that the condition can easily be fulfilled,with different values of the ratio NP/NR by selecting adifferent number of turns on the two windings (seeFigure 21). This provides an additional degree offreedom in the design of the system.Replacing NP in Equation 81 and neglecting VD, on,results in Equation 87.EQUATION 87:N SV OUT= -----------------------------------F PWMA coreΔBNR can be determined by considering the behaviordescribed in Figure 21.© 2009 Microchip Technology Inc. DS01207B-page 23

AN1207FIGURE 21:FORWARD CONVERTER: VOLTAGE ON THE MOSFET FOR DIFFERENT VALUESOF PRIMARY AND RESET WINDING TURNSTT/2 T/2t⎛ N1 P ⎞⎜ +------- ⎟ VDC⎝ N R ⎠A2NP = NRVDCA1TRtTON⎛ N1 P ⎞⎜ +------- ⎟ VDC > 2V⎝ N R ⎠ DCA2NP > NRVDCA1TONTRt⎛ N1 P ⎞⎜ +------- ⎟ VDC < 2V⎝ N R ⎠ DCVDCA2NP < NRA1TRtTONDS01207B-page 24© 2009 Microchip Technology Inc.

AN1207FIGURE 22:FORWARD CONVERTER WAVEFORMS (NP = NR): PRIMARY SIDETONTRQ1 CommandVDC – VQ, onTONTON + TRTt(A)VPt(B)IMt(C)VRt(D)IR = ID1t(E)N P⎛ ⎞ VDC(A) = Command signal on Q1 MOSFET gate1 + ------⎝ ⎠N RVDCVQ1A1A2t(F)IPIQ, mrt(G)(B) = Voltage VP on primary winding NP(C) = Magnetizing current IM(D) = Voltage VR on reset winding NR(E) = Reset winding current, equal to diode D1 current(F) = Voltage on Q1 MOSFET(G) = Primary winding current, equal to Q1 MOSFET current© 2009 Microchip Technology Inc. DS01207B-page 25

AN1207TRANSFORMER: PRIMARY, WIRE SIZEAs shown in Figure 22(G) the total current flowing intothe primary has two contributions: the magnetizing current(Equation 67) and the load current (Equation 72)reflected back into the primary, resulting inEquation 88.EQUATION 88:------ ( VV DC– V Q,onN SN DC– V Q,on)– V D, on– V OUT,------------------------------t ------ P=+ ---------------------------------------------------------------------------------tI P totalL MN PN SL OThe primary wire size can then be computed by firstreferring to Figure 22(G), and then replacing the realcurrent waveform with a pulse having a square shapedwaveform, with the same width and whose amplitude isthe value in the middle of the ramp (IQ, mr). The currentis expressed as a function of known (designrequirements) data.Note that in these computations, magnetizing current isneglected since the transformer is designed to make itabout one-tenth of the load reflected current.Therefore, the input power PI equals Equation 89.EQUATION 89:P IThe output power is shown in Equation 90.EQUATION 90:Solving Equation 90 results in Equation 91.EQUATION 91:This is the equivalent current flowing in the primarywires when TON is at its maximum allowed value. Therms value is computed in Equation 92.EQUATION 92:=V DC, minI Q, mrD maxP O= ηP I= ηV DC minwhere η is the converter efficiencyI Q, rmsI Q mr,I Q, mrD max1 PI Q, mr-- O=V DC,minD max⎛--------------------⎞ 1------------η⎝⎠P O1= ,D max= -- ⎛--------------------⎞----------------η⎝⎠V DC,minD maxD maxTRANSFORMER: SECONDARY, WIRE SIZEAs shown in Figure 24(C), the secondary currentequals the inductor current (IO, av) during TON.Again, as for the primary current, the actual currentwaveform is replaced with a current pulse having asquare shaped wave form whose amplitude equalsthe mid-ramp inductor current in the up-slope, IO, av,nom.Therefore, the secondary average current is equal toEquation 93.EQUATION 93:The rms value is computed as Equation 94.EQUATION 94:TRANSFORMER: RESET WINDING, WIRESIZEThe reset winding is not involved in carrying any currentreflected back into the primary from the secondary.The only current it has to carry is the magnetizing current,which is plotted in Figure 22(C). The magnetizingpeak current computed in Equation 67 is shown inEquation 95.EQUATION 95:I Sav ,= I O,av,nomI Srms ,= I O, av,nomD max–--------------------------------------------T ONV DCmin ( , )V Q,onI M, pk=L MThe rms value is the peak value multiplied by thesquare root of the duty cycle and divided by radix 3, asshown in Equation 96.The correct AWG (wire size) can be determinedaccordingly.DS01207B-page 26© 2009 Microchip Technology Inc.

AN1207EQUATION 96:( – )--------------------------------------------- ----------------T ON3V DC, minV Q,onI M, rms=L MD maxMOSFETDuring TOFF, the voltage on the Q switch is equal toEquation 97.EQUATION 97:⎛⎝V Q, off= 1N P ⎞N R⎠ VDC+ ------At t = TON, a spike due to leakage current appears. Itcan safely be estimated to be 30% of the peak value,as shown in Equation 98.EQUATION 98:,= 1.3 ⋅ ⎛1+ ------ ⎞⎝ ⎠V Q off,maxN PN RV DC,maxThe average current flowing through the switch hasbeen computed in Equation 92.DIODESTable 1 summarizes the values of average current andvoltage the diodes have to cope with.TABLE 1:DiodeD1DIODE CURRENT AND VOLTAGEConfiguration0 - TON TON - (TON + TR) (TON + TR) - TV D, max1N R= – ⎛ + ------ ⎞⎝ ⎠V DC,maxV FV D max=N P,– V DC,maxD2V FN SV D, max≈ ------N R– V DC,maxV D, max≈ 0D3Legend:N SV D, max------N PVF is the diode forward voltage.≈ – V DC,maxV FV F© 2009 Microchip Technology Inc. DS01207B-page 27

AN1207OUTPUT FILTER INDUCTORAs in all other topologies with an LC low-pass filter atthe output, the inductor is selected to not operate thesystem in Discontinuous mode. The inductor is calculatedjust at the edge between Continuous and Discontinuousmode (i.e., Critical mode), where the inductorcurrent starts from zero at the beginning of the PWMperiod and returns to zero before the PWM periodends. In this condition, the average current equals 0.5the peak current (or current ripple), as shown inFigure 23.FIGURE 23:INDUCTOR CURRENT: PEAK CURRENT, RIPPLE CURRENT AMPLITUDE ANDOUTPUT CURRENT AT THE EDGE OF DISCONTINUOUS MODEI InductorIO, PNIO, av, minIRIPPLETONTON + TRtIn Critical mode, the minimum acceptable outputcurrent (defined by design requirements) is madecoincident with the average current, as shown inEquation 99.EQUATION 99:Using Equation 72 to compute IO, ripple, results inEquation 100.EQUATION 100:L OOUTPUT CAPACITORI O, rippleI O, av,min= --------------------2N SN P------V DC, min– V OUT= ---------------------------------------------D2F PWMI maxO,av,minThe output voltage ripple is mainly due to the capacitorESR. The inductor current ripple flowing through it,determines a voltage drop. Therefore, a capacitor withan ESR equal to Equation 101 must be selected.EQUATION 101:The capacitor value itself can then be computed withEquation 102, which describes the value of the voltageripple taking into account all components.EQUATION 102:Neglecting ESL, since it is normally very small (at leastfor PWM frequencies less than 400 kHz), results inEquation 103.EQUATION 103:V OUT,rippleI O,rippleESR < ----------------------------where I O, ripple is computed as in Equation 98V rippleC OD maxESL ⋅ FI rippleESR ------------------PWM= ⎛ + + -----------------------------⎞⎝ F PWMC⎠I O, rippleD maxD max= ---------------------------------------------------------------------------------------F PWM( V OUT, ripple– I O, rippleESR)DS01207B-page 28© 2009 Microchip Technology Inc.

AN1207FIGURE 24:FORWARD CONVERTER WAVEFORMS: SECONDARY SIDETTONTRQ1 Commandt(A)TOFFVSt(B)IO, avIS = ID2t(C)VB = VD3t(D)VD2t(E)VLt(F)ILt(G)ID3t(H)(A) = Command signal on Q1 MOSFET gate(B) = Voltage VS on secondary winding NS(C) = Secondary winding current, equal to diode D2 current(D) = Voltage at node B(E) = Voltage on diode D2(F) = Voltage on LO inductor(G) = Current in LO inductor(H) = Current in diode D3© 2009 Microchip Technology Inc. DS01207B-page 29

AN1207TWO-SWITCH FORWARDCONVERTERClearly derived from the single-ended topology(Forward Converter), this circuit has significantadvantages over single-ended forward converters. Aschematic of this topology is shown in Figure 25.FIGURE 25:TWO-SWITCH FORWARD CONVERTER TOPOLOGYQ1D3VBVLVDCD2D1NPNSVSD4LOCOVOUTQ2Topology EquationsReferring to the section on Two-Switch ForwardConverters in AN1114 (see “Introduction”), the basicequations are reviewed first followed by the selection ofcircuit components.Both switches, Q1 and Q2, are simultaneously drivenby a square wave signal with a duty cycle less than 0.5,as shown in Figure 26.FIGURE 26:SIGNAL DRIVING SWITCHES Q1 AND Q2TRQ1 CommandQ2 CommandTONTDS01207B-page 30© 2009 Microchip Technology Inc.

AN1207Q1 ON, Q2 ON (INTERVAL 0 - TON)In this configuration, the circuit is redrawn, as shown inFigure 27.FIGURE 27:TWO-SWITCH FORWARD CONVERTER TOPOLOGY: INTERVAL 0 - TONIPRIMARYQ1D3VBVLVDCD2D1NPNSVSD4LOCOVOUTQ2Input Circuit BehaviorThe transformer is connected between VDC andground; the dot end is more positive than the non-dotend and the magnetizing current is flowing through it.Both diodes at the primary are reverse-biased and donot contribute to the operation.The voltage on the primary is equal to Equation 104.EQUATION 104:The secondary voltage is equal to Equation 106.EQUATION 106:V SN S= ------ ( V DC– 2V Q,on)N PEquation 107 shows the voltage on the inductor.EQUATION 107:V P= V DC– 2V Q,onV L=N S------ ( V DC– 2V Q,on) VN P– D, on– V OUTThe magnetizing current in the transformer has apositive slope increase as shown in Figure 30(C):EQUATION 105:I M() t( )= -------------------------------------- tV DC– 2V Q,onL MThe total current in the primary is this magnetizingcurrent plus the secondary current reflected by thetransformer back to the primary.Output Circuit BehaviorSimilar to the primary, the secondary winding experiencesa voltage that is higher at the dot end comparedto the non-dot end. Therefore, diode D3 is forwardbiasedand conducting the current to the inductor, whilediode D4 is reversed-biased.As shown in Equation 108, the current in the inductorhas a linearly growing behavior (see alsoFigure 31(E)).EQUATION 108:N S------ ( VN DC– 2V Q,on)– V D, on– V OUTPI L() t = I L( 0)+ ----------------------------------------------------------------------------------tAt this point, the total current in the primary windingscan be computed as the sum of the magnetizing currentand the secondary current reflected back into theprimary (see Figure 30(F)), as shown in Equation 109.L OEQUATION 109:I P, total() t = I L( 0)------ ( V( ) N-------------------------------------- ------ SN DC– 2V Q,on)– V D, on– V OUTP+ + ----------------------------------------------------------------------------------tV DC– 2V Q,onL MN PN SL O© 2009 Microchip Technology Inc. DS01207B-page 31

AN1207Q1 OFF Q2 OFF(INTERVAL TON TO (TON + TR))When both switches turn off, the magnetizing current inNP reverses all the voltages in the system. At the primary,the non-dot end part of the inductor becomesmore positive than the dot end (see Figure 28). Bothdiodes are forward-biased, which provides a path forthe leakage current, from the non-dot end of the primary,through D2 into the positive of VDC out of its negativewire, through diode D1, and back again to thetransformer.FIGURE 28:TWO-SWITCH FORWARD CONVERTER TOPOLOGY: INTERVAL TON - (TON + TR)Q1D3V BVLVDCD2D1VPNPNSVSD4LOCOVOUTQ2The voltage on the primary is equal to Equation 110.EQUATION 110:V P offThe magnetizing current can be expressed asEquation 111.EQUATION 111:,= –( V DC+ 2V D,on)I M() t–( )= ------------------------------------------tV DC+ 2V D,onL MThe magnetizing current reaches zero (that is, all theenergy stored into the transformer primary during TONhas been delivered back to the VDC input) at timeTON +TR, being (TON + TR) < T.Output Circuit BehaviorBecause of the change in polarity of the voltages dueto the magnetizing current, the polarity of the inducedsecondary voltage is such that the non-dot end of thewinding is more positive than the dot end. In the meanwhile,the voltage on the output inductor changes polarityas well, and its left side tries to go very negative, butis clamped to a diode voltage drop below ground bydiode D4, which is forward-biased. D3 on the contrarybecomes reverse-biased. The inductor current has itspath through diode D4 and into the load and the outputcapacitor.Equation 112 shows the secondary voltage.EQUATION 112:V SEquation 113 shows the inductor voltage.EQUATION 113:Equation 114 shows the current.EQUATION 114:N------ SN P= – ( V DC+ 2V D,on)V LI L() t= – V OUT– V D,on–( )= ------------------------------------------tV OUT+ V D,onL ODS01207B-page 32© 2009 Microchip Technology Inc.

AN1207Q1 OFF Q2 OFF (INTERVAL (TON + TR) TO T)As seen previously from (TON + TR) to T, there is nomore energy in the transformer primary, the magnetizingcurrent is zero and consequently the two diodes D1and D2 are not conducting any more, as they arereverse-biased.In this configuration, the circuit is redrawn as shown inFigure 29. Voltage VP and VS are both zero and voltageon the switch will be less than VDC. Nothing changes atthe secondary.FIGURE 29:TWO-SWITCH FORWARD CONVERTER TOPOLOGY: INTERVAL (TON + TR) - TQ1D3V BVLVDCD2D1VPNPNSVSD4LOCOVOUTQ2Design Equations and ComponentSelectionINPUT/OUTPUT RELATIONSHIP AND DUTYCYCLEThe input/output relationship is shown in Equation 115,and is obtained by equating Equation 108 withEquation 114, where t = TON and t = TOFF, respectively.EQUATION 115:V OUTN S= ------ ( V DC– 2V )D V Q,on– D , onN PEQUATION 117:D max, theoretical= 0.5Of course the real duty cycle will be somewhat smallerthan the maximum, theoretical value, to take intoaccount tolerances in the computations.TRANSFORMER: PRIMARYThe number of primary turns is determined from theFaraday equation shown in Equation 118, which resultsin Equation 119.Neglecting VD and VQ, the duty cycle can bedetermined, as shown in Equation 116.EQUATION 116:EQUATION 118:ΔB=V PT------------------- ONN PA coreV OUT=N S------V DCDN PEQUATION 119:The maximum theoretical duty cycle (Equation 117)can be obtained equating the two magnetizing currents(Equation 105 and Equation 111), considering that TRcan be at maximum TR = TOFF.N P( V DC, min– 2V Q,on)D max= --------------------------------------------------------------F PWMA coreΔB© 2009 Microchip Technology Inc. DS01207B-page 33

AN1207TRANSFORMER: PRIMARY, WIRE SIZEThe current flowing through the transformer can becomputed replacing the current in Figure 30(F), with anequivalent waveform having a constant amplitude (IP,mr), corresponding to the mid-ramp value.Considering the relationship of Equation 120 (betweenthe input power) and Equation 121 (the output power),this results in Equation 122. Therefore, the rms value isthen equal to Equation 123.EQUATION 120:TRANSFORMER: SECONDARY, WIRE SIZEBy referring to Figure 31(C), the current flowing into thesecondary winding can be determined, and the rampon a step current waveform can be approximated witha constant amplitude signal, being the amplitude IO, av,nom. Based on these, the corresponding rms value isequal to Equation 125.EQUATION 125:I SECONDARY, rms= I O, ar,nomD maxP O=ηP IMOSFETEQUATION 121:The maximum voltage the switches must be able towithstand during TOFF, is shown in Equation 126.P I=V DC, minI P, mrD maxEQUATION 126:EQUATION 122:EQUATION 123:P OI P, mr= -------------------------------------ηV DC, minD maxI P, rms= I P, mrD maxThe maximum current during TON is shown inEquation 127, which is the same current flowing intothe transformer.EQUATION 127:V Q, max≈ V DC,maxP OI P, mr= -------------------------------------ηV DC, minD maxTRANSFORMER: SECONDARYThe number of turns are determined by Equation 115and Equation 119 and results in Equation 124.EQUATION 124:N S=V OUT-----------------------------------F PWMA coreΔBDS01207B-page 34© 2009 Microchip Technology Inc.

AN1207FIGURE 30:TWO-SWITCH FORWARD CONVERTER WAVEFORMS: PRIMARY SIDETRQ1 CommandQ2 CommandTONTt(A)VPt(B)IMt(C)VDCVQ1, VQ2t(D)VD1, VD2t(E)IP, mrIPt(F)(A) = Command signal on Q1 and Q2 MOSFET gates(B) = Voltage VP on primary winding NP(C) = Magnetizing current IM(D) = Voltage on Q1 and Q2 MOSFETS(E) = Voltage on diodes D1 and D2(F) = Total primary current IP (magnetizing current and load current reflected back to the primary side of thetransformer)© 2009 Microchip Technology Inc. DS01207B-page 35

AN1207FIGURE 31:TWO-SWITCH FORWARD CONVERTER WAVEFORMS: SECONDARY SIDETRQ1 CommandQ2 CommandTONTON + TRt(A)VSt(B)ISt(C)VLt(D)IO, av, nomILt(E)IO, av, nomID3t(F)VD4t(G)ID4t(H)T(A) = Command signal on Q1 and Q2 MOSFET gates(B) = Voltage VS on secondary winding NS(C) = Current flowing into the secondary winding NS(D) = Voltage on inductor LO(E) = Current in inductor LO(F) = Current flowing in diode D3(G) = Voltage on diode D4(H) = Current in diode D4DS01207B-page 36© 2009 Microchip Technology Inc.

AN1207DIODESTable 2 provides calculations for determining diodevoltage.TABLE 2:DiodeD1V RDIODE VOLTAGEConfiguration0 - TON TON -> (TON + TR) (TON + TR) -> T= – V DC, max+ V Q,onV FV – V DC maxR= ------------------------,2D2D3V R= – V DC, max+ V Q,onV FV – V DC maxR= ------------------------VN SF VR = ------ ( V DC, max+ 2V Don ,) + V ≅ V D,onFN P,2D4V RN S= ------ ( V DC, max– 2V Qon ,) + V D,onN PV FV FLegend:VF is the diode forward voltage.Table 3 provides calculations for determining averagediode current.TABLE 3:DiodeD1D2D3D4DIODE CURRENTConfiguration0 - TON TON -> (TON + TR) (TON + TR) -> T00P O------------------------------------- 0ηV DC, minD maxP O------------------------------------- 0ηV DC, minD maxI O, av,nom0 00 I O av,nom,I O,av,nom© 2009 Microchip Technology Inc. DS01207B-page 37

AN1207OUTPUT INDUCTANCEThe output inductor is computed so that the outputinductor is at the edge of the Discontinuous mode whenthe output current is the minimum required (IO, av, min).Using the same approach used for the Forward Converter(see Figure 26 and Equations 99 and 100), fromEquation 108 and Equation 128 (neglecting the voltagedrops on the MOSFETS and diodes) results inEquation 129.EQUATION 128:I O, rippleI O, av,min= --------------------2EQUATION 129:L ON SN POUTPUT CAPACITANCE⎛------V DC, min– V ⎞⎝ODmax⎠= ---------------------------------------------------------2F PWMI O,av,minThe capacitance should present the lowest possibleimpedance at the frequency of the current ripple, toachieve the lowest output voltage ripple.The voltage ripple is determined by the ESR of the outputcapacitor and by the voltage drop on CO due to thecurrent flowing through it (see Equation 130).EQUATION 130:,= ESR ⋅ I O ripple+ ------ I O ripple--------------V OUT ripple1,C OD,F PWMThe output capacitor value can be determined fromEquation 131.DS01207B-page 38© 2009 Microchip Technology Inc.

AN1207HALF-BRIDGE CONVERTERDesign EquationsFigure 32 presents the schematic of a Half-BridgeConverter. Please refer to the section on Half-BridgeConverters in AN1114 (see “Introduction”) for adetailed description of the operation of the system.The waveforms (two pulses, with adjustable width anda 180° phase delay) used to drive the gates of the twoQ transistors are represented in Figure 33. Some marginis needed after the falling edge of one pulse beforethe rising edge of the other. These time intervals arecalled TR. If not implemented, a short circuit exists andthe switches will be destroyed by the very high currentflowing through the path from VDC to ground. Initially,CB is replaced with a short circuit.FIGURE 32:HALF-BRIDGE CONVERTER TOPOLOGYVDC/2C1Q1D1NPNSD3VBVLLOVDCVDC/2C2CBQ2NSD4COROVOUTD2FIGURE 33:Q1 AND Q2 COMMAND SIGNALSTRTRSignalDriving Q1T1ONSignalDriving Q2TT2ON© 2009 Microchip Technology Inc. DS01207B-page 39

AN1207Q1 ON, Q2 OFFIn this configuration, the circuit is redrawn as shown inFigure 34.FIGURE 34:HALF-BRIDGE CONVERTER TOPOLOGY: Q1 ON, Q2 OFFVDC/2C1Q1D1NPNSD3VBVLLOVDCVPVSD4COROVOUTVDC/2C2Q2D2Input Circuit BehaviorThe voltage on capacitor C1 develops a voltage on theprimary circuit where the dot end is more positive thanthe non-dot end.Equation 132 shows the voltage at the primary.EQUATION 132:V PEquation 133 shows the magnetizing current.EQUATION 133:V DC= ⎛--------- – V ⎞⎝ 2 Q1,on ⎠I M() tV DC--------- V2 Q1,on= --------------------------- tL MOutput Circuit BehaviorBecause of the voltage polarity on the primary, the dotendedge of the secondary is more positive than thenon-dot end. Diode D4 is then reverse-biased and D3is forward-biased.Equation 134 shows the voltage at the secondary.EQUATION 134:V SEquation 135 shows the voltage on the inductor.EQUATION 135:V LN SN PN SN P------ V DC= ⎛--------- – V ⎞⎝ 2 Q1,on ⎠------ V DC= ⎛--------- – V ⎞⎝ 2 Q1,on– V⎠ D3, on– V OUT> 0Equation 137 shows the current.EQUATION 136:N S------ ⎛ V DC--------- – V ⎞N P2 Q1,on– V⎝⎠ D3, on– V OUTI L() t = I L( 0)+ ------------------------------------------------------------------------------------------ tL ODS01207B-page 40© 2009 Microchip Technology Inc.

AN1207Q1 OFF, Q2 ONIn this configuration, the circuit is redrawn as shown inFigure 35.FIGURE 35:HALF-BRIDGE CONVERTER TOPOLOGY: Q1 OFF, Q2 ONVDC/2C1Q1D1NPNSD3VBVLLOVDCVSD4COROVOUTVDC/2C2Q2D2Input Circuit BehaviorIn this instance, the dot end of the primary winding hasa voltage that is more negative than the non-dot end.Equation 137 shows the primary winding voltage.EQUATION 137:Output Circuit BehaviorAs with the primary, the dot end of the secondarywinding has a voltage more negative than the nondotend. As a consequence, D3 in open and D4 isforward-biased.Equation 139 shows the secondary voltage.V PV DC= – --------- + V2 Q,onEquation 138 shows the magnetizing current.EQUATION 139:V S=N S------ ⎛–--------- + V ⎞⎝ 2 Q,on ⎠N PV DCEQUATION 138:I M() t=V DC– --------- + V2 Q,on-----------------------------------tL MEquation 140 shows the inductor voltage.EQUATION 140:V LN S------ V DC= ⎛--------- – V ⎞⎝ 2 Q,on ⎠– V D on–N P,V OUTEquation 141 shows the current.EQUATION 141:N S------ ⎛V DC--------- – V ⎞N P⎝ 2 Q,on ⎠ – VD,on– V OUTI L() t = I L( T ON) + ---------------------------------------------------------------------------------- tL O© 2009 Microchip Technology Inc. DS01207B-page 41

AN1207Q1 OFF, Q2 OFF (PERIOD TR)In this configuration, the circuit is redrawn as shown inFigure 36.FIGURE 36:HALF-BRIDGE CONVERTER TOPOLOGY: Q1 OFF, Q2 OFFVDC/2C1Q1D1NPNSD3VBVLLOVDCVSD4COROVOUTVDC/2C2Q2D2Input Circuit BehaviorIn this instance, the current path in the primary sidewhen Q1 turns off (Figure 37) and when Q2 turns off(Figure 38).FIGURE 37:HALF-BRIDGECONVERTER: CURRENTPATH IN THE PRIMARY SIDEWHEN Q1 TURNS OFFOutput Circuit BehaviorWhen both switches are off, the voltage on the twosecondary windings are such that both D1 and D2 areforward-biased and are conducting. The current is splitequally between them, so that each of them isconducing one half of the current flowing into theinductor. The resulting current waveforms are shown inFigure 40.Equation 142 shows the inductor voltage.EQUATION 142:VDC/2C1Q1D5NPV L=– V OUTVDCVDC/2C2Q2D6< 0Equation 143 shows the current flowing through it.EQUATION 143:I L() t– V OUT= ----------------tL OFIGURE 38:HALF-BRIDGECONVERTER: CURRENTPATH IN THE PRIMARY SIDEWHEN Q2 TURNS OFFD5VDC/2C1Q1N PVDC> 0VDC/2C2Q2D6DS01207B-page 42© 2009 Microchip Technology Inc.

AN1207FIGURE 39:HALF-BRIDGE CONVERTER WAVEFORMS: PRIMARY SIDEQ1Commandt(A)Q2Commandt(B)VDC/2VPt(C)-VDC/2VDCVDC/2VQ1t(D)IP, mrIQ1t(E)VDCVDC/2VQ2t(F)IP, mrIQ2t(G)TONTRTONTRT(A) = Command signal on Q1 MOSFET gate(B) = Command signal on Q2 MOSFET gate(C) = Voltage VP on primary winding NP(D) = Voltage on Q1 MOSFET(F) = Current flowing in Q1 MOSFET(G) = Voltage on Q2 MOSFET(H) = Current flowing in Q2 MOSFET© 2009 Microchip Technology Inc. DS01207B-page 43

AN1207FIGURE 40:HALF-BRIDGE CONVERTER WAVEFORMS: SECONDARY SIDEQ1 Commandt(A)Q2 Commandt(B)NP/NS VDC/2VS-NS/NP VDC/2NS/NP VDCVD3tt(C)(D)ID3t(E)VD4t(F)ID4t(G)VLt(H)IO, av, nomILt(I)(A) = Command signal on Q1 MOSFET gate(B) = Command signal on Q2 MOSFET gate(C) = Voltage V S on secondary winding NS(D) = Voltage on diode D3(E) = Current flowing in diode D3(F) = Voltage on diode D4(G) = Current flowing in diode D4(H) = Voltage on inductor LO(I) = Current in inductor LODS01207B-page 44© 2009 Microchip Technology Inc.

AN1207Design Equations and ComponentSelectionINPUT/OUTPUT RELATIONSHIP AND DUTYCYCLEAt the Steady state, the increase in inductor currentduring TON must equal its decrease during TR (neglectingthe forward drop on the diode), as shown inEquation 144.EQUATION 144:Equation 147 shows the input power.EQUATION 147:Equation 148 shows the output power.EQUATION 148:P I=V--------- DCI2 P, mr2DP O= ηP IV OUT=N S------V DCDN Pwhere η is the efficiencywhere DT ON= --------- , and ( TTON+ T R)=T--2Operating on these two equations results inEquation 149.Consequently, knowing that there are two pulses in thePWM period, the maximum theoretical duty cycle isDmax, theoretical = 0.5. Of course, to avoid the shootthroughin the two switches, the maximum duty cyclecorresponding to the minimum input voltage, will beless.TRANSFORMER: PRIMARYAs soon as the transformer core has been defined, theprimary turns number can be computed from Faraday’slaw as shown in Equation 145, resulting inEquation 146.EQUATION 149:P OI P, mr= -------------------------------------ηV DC, minD maxEquation 150 shows the rms value.EQUATION 150:I P, rms= I P, mrD maxEQUATION 145:TRANSFORMER: SECONDARY, NUMBER OFTURNS, WIRE SIZEΔBV PT ON= -------------------N PA coreThe secondary turns number shown in Equation 151,can be obtained from Equation 144 and Equation 146.EQUATION 146:EQUATION 151:N P=V DC, minD max---------------------------------------2F PWMA coreΔBN S=V OUT---------------------------------------2F PWMA coreΔBTRANSFORMER: PRIMARY, WIRE SIZECurrent flowing in the primary windings is plotted inFigure 39(E and G). It is the sum of the magnetizingcurrent flowing into the primary windings and the secondaryload current reflected back by the transformerturn ratio.To make computations simpler, the real current waveformscan be replaced with the mid-ramp value (IP, mr)and determine its value considering the input (PI) andoutput (PO) power.The average output current, shown as IO, av, nom inFigure 40(I), is the average output current the converteris designed for. The rms secondary current (IS)results in Equation 152.EQUATION 152:I Srms ,= I O, av,nomD max© 2009 Microchip Technology Inc. DS01207B-page 45

AN1207SWITCHESReferring to section on Half-Bridge Converters inAN1114 (see “Introduction”), one of the mainadvantages of the Half-Bridge Converter topology isthat the switches must withstand a maximum voltagethat is VDC, compared to 2 VDC as in push-pulltopologies. During TON and TR, the Q1 and Q2 switchesare subject to a maximum voltage of VQ, max = VDC,max.The maximum current flowing through the switches hasalready been computed in Equation 150.OUTPUT INDUCTANCEThe inductor is selected in such a way as to prevent theoutput inductor current from becoming discontinuous.The computations are performed at the edge betweencontinuous and discontinuous operation, when theoutput starts from zero at the beginning of the TONperiod and goes back to zero at the end of the TRperiod. In other words, the inductor current peak (whichis also the current ripple, DI) is twice the output averagecurrent (see Equation 153).EQUATION 153:N SN PI O, ripple= 2I O, a( v,min)=Equation 154 shows the results.EQUATION 154:------ VDC ,-------------------- min – V2 OUT----------------------------------------------- T ONL OOUTPUT CAPACITORThe output voltage ripple is mainly due to the ESR,which results in Equation 155.EQUATION 155:,= ESR ⋅ I O ripple+ ------ I O ripple--------------V OUT rippleAs previously seen in other topologies, the outputcapacitor value can be determined from the relationshown in Equation 156.EQUATION 156:C OCAPACITOR CBCapacitor CB (see Figure 32) is used to block the DCcomponent of the current flowing into the transformer toavoid core saturation. Small differences between C1and C2 create an unbalance of the voltage at the pointbetween them and causes the core to walk along thehysteresis loop onto saturation.The presence of the small capacitor causes a droop inthe primary voltage. The voltage during TON will decayalmost linearly with time.Assuming ΔVD is the maximum acceptable droopvoltage, which results in Equation 157.EQUATION 157:1,C OI O, rippleD maxD,F PWM= ---------------------------------------------------------------------------------------F PWM( V OUT, ripple– I O, rippleESR)L O=N SN ------ VDC ,-------------------- min – VP2 OUT----------------------------------------------- D2F PWMI maxO,av,minC BI P mr> ------------ T ONΔ,V DDS01207B-page 46© 2009 Microchip Technology Inc.

AN1207PUSH-PULL CONVERTERThe Push-Pull Converter uses a transformer to isolatethe input from the output circuit.Topology EquationsFigure 41 shows the schematic of a Push-PullConverter. Refer to AN1114 (see “Introduction”) for adetailed description of the system operation.The waveforms (two pulses, with adjustable width andwith a 180° phase delay) used to drive the gates of thetwo Q transistors are shown in Figure 42. T is theperiod of the waveform, with two pulses in T, one on Q1and the second one on Q2. This means that the dutycycle must be less than 0.5 to prevent overlap of thetwo pulses. Some margin is needed after the fallingedge of one pulse before the rising edge of the other.These time intervals are called TR.FIGURE 41:PUSH-PULL CONVERTER TOPOLOGYD2VAVLVDCVDCNPVP1NPVP2NSVS1N SVS2D1LOCOROVOUTQ1Q2FIGURE 42:SIGNALS DRIVING Q1 AND Q2 MOSFET GATESTRTRSignalDriving Q1T1ONSignalDriving Q2TT2ON© 2009 Microchip Technology Inc. DS01207B-page 47

AN1207Q1 ON, Q2 OFFIn this configuration, the circuit is redrawn as shown inFigure 43.FIGURE 43:PUSH-PULL CONVERTER: Q1 ON, Q2 OFFVLD2VAVDCVDCNPVP1NPVP2NSVS1NSVS2D1LOCOROVOUTQ1Q2Input Circuit BehaviorThe input voltage VDC gives place to a voltage on theprimary winding where the non-dot ends are morepositive than the dot-ends.Equation 158 shows the voltage at the primary.EQUATION 158:This same voltage is present on the lower primarywinding (supposing NP1 = NP2), so that the totalvoltage on Q2 switch is equal to Equation 159.EQUATION 159:V P= –( V DC– V Q1,on)Output Circuit BehaviorBecause of the voltage polarity on the primary, the dotends of the secondary is more negative that the nondotend. Diode D2 is then reverse-biased and D1 isforward-biased.Equation 161 shows the voltage at the secondary.EQUATION 161:V SEquation 162 shows the voltage on the inductor.EQUATION 162:N------ SN P= – ( V DC– V Q1,on)V Q2 off,= 2V DC– V Q1,onV L=N S------ ( V DC– V ) V Q1,on– D1 ,– V on OUT> 0N PEquation 160 shows the magnetizing current.EQUATION 160:I M() t– V DC+ V Q,on= ----------------------------------tL MEquation 163 shows the current.EQUATION 163:N S------N ( V DC– V ) Q1,on– V D1 ,– V on OUTPI L() t = I L( 0)+ -------------------------------------------------------------------------------------- tL ODS01207B-page 48© 2009 Microchip Technology Inc.

AN1207Q1 OFF, Q2 ONIn this configuration, the circuit is redrawn as shown inFigure 44.FIGURE 44:PUSH-PULL CONVERTER: Q1 OFF, Q2 ONVLD2VBVDCVDCNPVP1NPVP2NSVS1NSVS2D1LOCOROVOUTQ1Q2Input Circuit BehaviorIn this instance, the dot end of the primary windings hasa voltage more positive than the non-dot end.Equation 164 shows the primary winding voltage.EQUATION 164:V P= V DC– V Q2,onOutput Circuit BehaviorAs with the primary, the dot end of the secondarywindings has a voltage more positive than the nondotend. As a consequence, D1 is open and D2 isforward-biased.Equation 166 shows the secondary voltage.EQUATION 166:Equation 165 shows the magnetizing current.V S=N S------ ( V DC– V Q2,on)N PEQUATION 165:I M() tV DC– V Q,onL M= ------------------------------ tEquation 167 shows the inductor voltage.EQUATION 167:V LN S= ------ ( V DC– V ) V Q2,on– D2 ,– V on OUT> 0N PEquation 168 shows the current.EQUATION 168:N S------N ( V DC– V ) Q2,on– V D2 ,– V on OUTPI L() t = I L( 0)+ ----------------------------------------------------------------------------------------- tL O© 2009 Microchip Technology Inc. DS01207B-page 49

AN1207Q1 OFF, Q2 OFF (PERIOD TR)In this configuration, the circuit is redrawn as shown inFigure 45.FIGURE 45:PUSH-PULL CONVERTER: Q1 OFF, Q2 OFFVLD2VAVDCVDCNPVP1NPVP2NSVS1NSVS2D1LOCOROVOUTQ1Q2Input Circuit BehaviorEquation 169 shows the voltage on each switch.EQUATION 169:Output Circuit BehaviorWhen both switches are off, since the current in theinductor continues to flow in the same direction asbefore, the voltage on the two secondary windings aresuch that: Vs2 = -Vs1, and D1 and D2 are forwardbiasedand are conducting. They split the currentequally, so that each of them is conducting one half ofthe current flowing into the inductor. The resulting currentwaveforms are plotted in Figure 47(G and H) forthe two secondary windings currents.Equation 170 shows the inductor voltage.EQUATION 170:V LBased on Equation 170, the current flowing through theinductor LO is equal to Equation 171.EQUATION 171:V Q=V DC= – V OUT– V D on+,V S1where V S1 is IL times the resistance of the windings(almost zero).– V OUT– V D,onI L() t = I L() t + --------------------------------------tL ODesign Equations and ComponentSelectionINPUT/OUTPUT RELATIONSHIP AND DUTYCYCLEAt the Steady state, the increase in inductor currentduring TON must equal its decrease during TR. UsingEquation 168 and Equation 171 (neglecting the forwarddrop on the diode) and since (TON + TR) = T/2,results in Equation 172.EQUATION 172:where D =V OUTT--------- ONTConsequently, knowing there are two pulses in thePWM period, the maximum theoretical duty cycle canbe Dmax = 0.5.Starting from the input/output relationship shown inEquation 173, the feedback control loop keeps the outputvoltage VOUT constant against changes in the inputvoltage VDC, and if VDC decreases, TON will increase tocompensate.EQUATION 173:V OUT2 N S= ------ ( V DC– V Q1,on)DN P2 N S------ ( V DC– V Q1,on) T ON=---------TN PTherefore, for the system design, a maximum dutycycle (Dmax) can be defined that corresponds to theminimum input voltage (VDC, min) and if less than themaximum, theoretical is equal to Equation 174.EQUATION 174:D maxN PV OUT= ------------------------------2N SV DC,minDS01207B-page 50© 2009 Microchip Technology Inc.

AN1207TRANSFORMER: PRIMARY, NUMBER OFTURNSAs clearly stated in the Push-Pull Converter section inAN1114 (see “Introduction”), the operating point ofthe core transformer moves between points that are inthe first and third quadrant of the hysteresis loop.Once the maximum allowable ΔB has been defined(based on PWM frequency and geometrical dimensionsof the core and bobbins), using the Faradayequation shown in Equation 158 and Equation 175,results in the number of primary turns, as shown inEquation 176.EQUATION 175:TRANSFORMER: PRIMARY, WIRE SIZECurrent flowing in the primary windings and into theswitches are plotted in Figure 46(G and H).To simplify computations, the real current waveformscan be replaced with the mid-ramp value (IP, mr) anddetermine its value considering the input (PI) andoutput (PO) power.The input power is shown in Equation 177.EQUATION 177:P I=where D is the duty cycleV DCmin ( , )I P, mr2D maxΔB=V PT------------------- ONN PA coreThe output power is shown in Equation 178.EQUATION 178:EQUATION 176:P O=ηP IN P=---------------------------------------------D ( V DC, min– V Q,on)A coreF PWMΔBmaxwhereη is the efficiencyOperating on these two equations results inEquation 179.EQUATION 179:P OI P, mr= ----------------------------------------2ηV DC, minD maxThe rms value is shown in Equation 180.EQUATION 180:I P, rms= I P, mrD max© 2009 Microchip Technology Inc. DS01207B-page 51

AN1207FIGURE 46:PUSH-PULL CONVERTER WAVEFORMS: PRIMARY SIDEQ1 Commandt(A)Q2 Commandt(B)VP1t(C)VP2t(D)VQ1t(E)2VDCVDCVQ2t(F)IP, mrIQ1t(G)IP, mrIQ2t(H)(A) = Command signal on Q1 MOSFET gate(B) = Command signal on Q2 MOSFET gate(C) = Voltage VP1 on primary winding NP (upper half)(D) = Voltage VP2 on primary winding NP (lower half)(E) = Voltage on Q1 MOSFET(F) = Voltage on Q2 MOSFET(G) = Current flowing in Q1 MOSFET(H) = Current flowing in Q2 MOSFETDS01207B-page 52© 2009 Microchip Technology Inc.

AN1207TRANSFORMER: SECONDARY, NUMBER OFTURNSOnce the primary number of turns has been defined,NS can be determined using Equation 173 andEquation 176, as shown in Equation 181.EQUATION 181:MOSFETSIn Equation 159 (repeated in Equation 184) the voltagethe switch must be able to withstand (considering themaximum input voltage) twice the maximum inputvoltage.EQUATION 184:N S=V OUT2A --------------------------------------- ⋅coreF PWMΔB10 8V Q2, off= 2V DC, max– V Q1,onTRANSFORMER: SECONDARY, WIRE SIZEAs previously seen, the secondary current waveform isquite complex (refer to Figure 47(G and H). However,to simplify computations, a contribution to the currentonly during TON is considered. The average current,shown as IO, av, nom, is the average output current theconverter is designed for. The rms secondary current(IS) results in Equation 182.EQUATION 182:DIODESI Srms ,= I O, av,nomD maxDuring TON (Q1 ON, Q2 OFF), diode D2 is reversebiased.The maximum voltage it can tolerate is equal toEquation 183.The maximum voltage the switches have to withstandmust also take into account the spike that is generatedby leakage inductance on the falling edges of theswitch control signal. The spike is generally estimatedto be 30% higher than the voltage on the switch. Therefore,at the end of the TON time interval, the maximumvoltage is equal to Equation 185.EQUATION 185:V Q, max≈ 2.6V DC,maxThe maximum current flowing through the switches hasbeen already computed in Equation 179.The maximum VQ, max and IP, mr are now obtained.Therefore, almost all that is needed to make the bestdevice choice is known. All that remains is to add theanalysis of the power dissipated in the switch, whichare switching and DC losses.EQUATION 183:,2 N S= – ------ ( V DC, max– V Q1,on) + V D1V R D2N PThe average current flowing in D1 is the same currentthat is flowing into the inductor, and its value is IO, av,nom.During the other TON period (Q1 OFF, Q2 ON), thingsare reversed; now D1 is reverse-biased and D2 isconducting. The same values as before apply.© 2009 Microchip Technology Inc. DS01207B-page 53

AN1207FIGURE 47:PUSH-PULL CONVERTER WAVEFORMS: SECONDARY SIDEQ1 Commandt(A)Q2 Commandt(B)ID1t(C)ID2t(D)VLt(E)IO, av, nomILt(F)IO, av, nom/2IS(upper)t(G)IO, av, nom/2IS(lower)t(H)(A) = Command signal on Q1 MOSFET gate(B) = Command signal on Q2 MOSFET gate(C) = Current flowing in diode D1(D) = Current flowing in diode D2(E) = Voltage on inductor LO(F) = Current in inductor LO(G) = Current flowing in secondary winding (upper half)(H) = Current flowing in secondary winding (lower half)DS01207B-page 54© 2009 Microchip Technology Inc.

AN1207Switching LossesFigure 48 plots the current and voltage in the switch atthe switching instance. When the switch is turned on,the voltage falls rapidly, while the current has a smoothup-slope since current cannot change abruptly in aninductor. As seen in Figure 48, power dissipation iszero.Things are completely different when the switch isturned off. Both the voltage and the current have asmooth slope (an up-slope the former, a down-slopethe latter), and there is a significant overlap and somenon-zero power is dissipated.FIGURE 48:PUSH-PULL CONVERTER: SWITCHES, CURRENT AND VOLTAGEV2VDCIP, mrITSWTSWIts value can be easily computed using Equation 186.EQUATION 186:2V DC, maxT SWP Q, ac,max= I P, mrwhere T SW equals the rise and fall timesI P mr---------------------------------- ,T SW+ 2V2TDC,max---------------------- = 2I2T P mrT SW,V DC, max---------TThe DC losses can then be computed, as shown inEquation 187.EQUATION 187:P Q, dc, max= I P, mrV Q, onD maxThe total power dissipated in the switch is then equal toEquation 188.EQUATION 188:T SWP Q, total,max= P Q, ac+ P Q, dc= 2I P, mrV DC, max--------- + IT P mr,V Q, onD max© 2009 Microchip Technology Inc. DS01207B-page 55

AN1207OUTPUT INDUCTORThe inductor is selected in such a way as to prevent theoutput inductor current from becoming discontinuous.The computations are performed at the edge betweencontinuous and discontinuous operation, meaningwhen the output current starts from zero at the beginningof the TON period and goes back to zero at the endof the TR period. In other words, the inductor currentpeak, which is also the current ripple DL, is twice theoutput average current, as shown in Equation 189.EQUATION 189:N SN PI O, ripple= 2I O, av,min=------ ( V DCmin ( , )– V OUT)--------------------------------------------------------T ONL OSolving Equation 189 results in Equation 190.OUTPUT CAPACITORAs with the Buck Converter design, the output voltageripple is mainly due to the ESR, resulting inEquation 191.EQUATION 191:V OUT rippleAs seen in previous topologies, the output capacitorvalue can be determined from the relationship shown inEquation 192.EQUATION 192:C O,= ESR ⋅ I O,rippleI O, rippleD max= ---------------------------------------------------------------------------------------F PWM( V OUT, ripple– I O, rippleESR)EQUATION 190:L O=N S------VN DC, min– V OUTP-----------------------------------------------D2F PWMI maxO,av,minDS01207B-page 56© 2009 Microchip Technology Inc.

AN1207FULL-BRIDGE CONVERTERA Full-Bridge Converter, which is capable of managinghigher power levels, requires some additionalcomponents compared to the Half-Bridge Converter.Topology EquationsThe basic Full-Bridge Converter topology is shown inFigure 49. Transistors Q1, Q4 and Q2, Q3 are alwaysoperated together, driven by the waveform shown inFigure 50. Care must be taken so that Q1, Q2 or Q3,Q4 are not ON at the same time; otherwise, a lowimpedance path is created from VDC to ground. Thisimposes a maximum value on the TON interval as isdiscussed in a later section.FIGURE 49:FULL-BRIDGE CONVERTER TOPOLOGYVQ1Q1D1VQ3Q3D3NPNSVD5D5LOVDCCIVPVS1VS2D6VD6COVOUTVQ2Q2D2VQ4Q4D4NSFIGURE 50:FULL-BRIDGE CONVERTER WAVEFORMTTTOFFTONtTONTOFFt© 2009 Microchip Technology Inc. DS01207B-page 57

AN1207Q2 ON, Q3 ON; Q1 OFF, Q4 OFF(INTERVAL 0-TON)As shown in Figure 51, current flows through Q3, thetransformer primary and Q2 back to the input. The dotend of the transformer is more positive than the non-dotend.FIGURE 51:FULL-BRIDGE TOPOLOGY: Q2 AND Q3 ONVQ1Q1D1VQ3Q3D3NP NSVD5D5LOVDCCIVPVS1VS2D6VD6COVOUTVQ2Q2D2VQ4Q4D4NSInput Circuit BehaviorThe voltage on the primary is shown in Equation 193.EQUATION 193:The secondary voltage can be computed as shown inEquation 195.EQUATION 195:V P= V DC– V Q2 on–,V Q3 on,= V DC– 2V Q,onV S1N S= ------V P=N PN S------ ( V DC– 2V Q,on)N PThe magnetizing current increases according to the lawshown in Equation 194.Equation 196 shows the current flowing into theinductor.EQUATION 194:i M() tV P= ----- t =L PV DC–--------------------------------- t2V Q,onL PEQUATION 196:N S------VN DC– V OPi L() t = i L( 0)+ ------------------------------ tL OOutput Circuit BehaviorAs for the primary winding, the dot ends of the two secondarywindings are more positive that the two non-dotends. This implies that diode D5 is conducting whilediode D6 is not conducting.The voltage on the output capacitor LO is shown inEquation 197.EQUATION 197:N SV LV S1V D5, onV O------ ( V DC– 2V ) V N S= – – =Q,on– D5 ,– V on O≈ ------V DC– V O> 0N PN PDS01207B-page 58© 2009 Microchip Technology Inc.

AN1207Q1 ON, Q4 ON; Q2 OFF, Q3 OFF(INTERVAL 0-T ON )As shown in Figure 52, current flows through Q1, thetransformer, and Q4 back to the input. The dot end ofthe transformer is now more negative than the non-dotend.FIGURE 52:FULL-BRIDGE CONVERTER TOPOLOGY: Q1 AND Q4 ONVQ1Q1D1VQ3Q3D3NPNSVD5D5LOVDCCIVPVS1VS2D6VD6COVOUTVQ2Q2D2VQ4Q4D4NSInput Circuit BehaviorThe primary voltage is shown in Equation 198.EQUATION 198:Output Circuit BehaviorIn this instance, as at the primary, the dot ends aremore negative than the non-dot ends, which results inEquation 200.V P=– V DC+ V Q1 on+,V Q4, on= V– DC+ 2V Q,onEQUATION 200:The magnetizing current is shown in Equation 199.V S2N S= ------V P=N PN S–------( V DC– 2V Q,on)N PEQUATION 199:i M() tV P= ----- t =L P– V DC+ 2V Q,on-------------------------------------tL PThe output inductor voltage is shown in Equation 201.EQUATION 201:V LN S= ------ ( V DC– 2V Q,on) VN P– D6, on– V OThe current flowing through it is shown inEquation 202.EQUATION 202:N S------VN DC– V OPi L() t = i L( 0)+ ------------------------------ tL O© 2009 Microchip Technology Inc. DS01207B-page 59

AN1207Q2 AND Q3 HAVE JUST SWITCHED OFF; Q1AND Q4 ARE OFFWhen the switches are open, the magnetizing currentcontinues to flow, reversing all voltages. At the primary,the dot end becomes more negative than the non-dotend. The magnetizing current flows through D4, thetransformer, and D1 as seen in Figure 53.The voltage on the primary is zero, and as shown inEquation 203 the voltage on the secondary is:EQUATION 203:V S1= – V S2Consequently, both diodes D5 and D6 are ON and theinductor current is split in half between the two diodepaths (see Figure 53 and Figure 54).The voltage on the inductor is shown in Equation 204.EQUATION 204:V L= – V S2– V O– V D6, on≈ – V O– V D6,onSince VS2 is very low, its magnitude is given by the voltagedrop on the secondary winding resistance due toone half of the inductor current flowing through it.Q2 AND Q3 HAVE JUST SWITCHED OFF; Q1AND Q4 ARE OFFThe behavior is similar to the previous condition. Thecurrent path in the primary is shown in Figure 54.FIGURE 53:FULL-BRIDGE TOPOLOGY: Q2 AND Q3 HAVE JUST SWITCHED OFF;Q1 AND Q4 ARE OFF (PRIMARY CURRENT PATH)VQ1Q1D1VQ3Q3D3NPNSVD5D5LOVDCCIVPVS1VS2D6VD6COVOUTVQ2Q2D2VQ4Q4D4NSFIGURE 54:FULL-BRIDGE TOPOLOGY: Q1 AND Q4 HAVE JUST SWITCHED OFF;Q2 AND Q3 ARE OFF (PRIMARY CURRENT PATH)VQ1Q1D1VQ3Q3D3NPNSVD5D5LOVDCCIVPVS1VS2D6VD6CoVOUTVQ2Q2D2VQ4Q4D4NSDS01207B-page 60© 2009 Microchip Technology Inc.

AN1207Design Equations and ComponentSelectionINPUT/OUTPUT RELATIONSHIP AND DUTYCYCLEThe product of the primary voltage multiplied by TONmust equal the product of the voltage multiplied byTOFF.Computing Equation 197 and Equation 204 results inEquation 205.EQUATION 205:V O=N SN PTo guarantee that the two switches of a leg are neverON at the same time, TON is limited to be at a maximumpercentage of T, as shown in Equation 206.EQUATION 206:The resulting maximum duty cycle is shown inEquation 207.EQUATION 207:------ ( V DC– 2V Q,on) V– D D5, onwhere D =TON/T and the relationship TON +TOFF =T isused (see Figure 50)where, δ equals 0.8T ON, max= δTD MAX=T-------------------- ON, maxTThe primary winding turn can be computed from theequation that relates the core flux change (ΔB), thevoltage across the winding (VP) and the geometricalentity (A e ), as shown in Equation 209.EQUATION 209:N P=TRANSFORMER: PRIMARY, WIRE SIZESince the design specification POUT is known, the inputpower can be computed considering a converterefficiency of η, as shown in Equation 210.EQUATION 210:Solving Equation 210 results in Equation 211.EQUATION 211:With some approximation, and replacing the real currentwaveform (ramp on a step) with a constant valueequal to IIN, av, results in Equation 212.EQUATION 212:V P, maxT ON,maxV DC min-------------------------------------- ,D MAX≈ -----------------------------------ΔBA eΔBF PWMA eP OUT= ηP IN= ηV DC min,I IN, avδwhere I IN, av is the average input current(see Figure 55 (E,G,I,K)) and δ = 0.8P OUTI INav ( , )= ---------------------------ηV DC, minδI IN, av,rms= I IN, avD MAXTRANSFORMER WINDING TURN RATIOThe maximum TON period will occur when the inputvoltage is at its minimum. Using Equation 205 andEquation 206 results in Equation 207.EQUATION 208:N------ SN P=( V O+ V D5,on) T ON,max--------------------T----------------------------------------------------------------------( V DC, min– 2V Q,on) T ON,max--------------------T© 2009 Microchip Technology Inc. DS01207B-page 61

AN1207FIGURE 55:FULL-BRIDGE CONVERTER TOPOLOGY: INPUT CIRCUITTONTOFFTQ2 and Q3Commandt(A)TTONTOFFQ1 and Q4Commandt(B)VPt(C)VDC - VQ2, onVQ1t(D)IQ1VDC - VQ3, ont(E)VQ4t(F)IQ4VDC - VQ1, ont(G)VQ2t(H)IIN, AVIQ2VDC - VQ4, ont(I)VQ3IIN, avt(J)IQ3t(K)(A) = Q2 and Q3 switch the command signal(B) = Q1 and Q4 switch the command signal(C) = Primary voltage(D) = Voltage on MOSFET Q1(E) = Current flowing into MOSFET Q1(F) = Voltage on MOSFET Q4(G) = Current flowing into MOSFET Q4(H) = Voltage on MOSFET Q2(I) = Current flowing into MOSFET Q2(J) = Voltage on MOSFET Q3(K) = Current flowing into MOSFET Q3DS01207B-page 62© 2009 Microchip Technology Inc.

AN1207TRANSFORMER: SECONDARY, NUMBER OFTURNS, WIRE SIZEThe secondary number of turns can be computed fromEquation 208 and Equation 209 (see also Figure 56(Dand E)).To simplify the computation of the secondary rms currentvalue, we do not consider that the contribution tothe current value during TOFF is not calculated (this isdue to the relatively short interval and small value of thecurrents). The average value as the medium value duringthe ramp current is considered (see Figure 56(Dand E)).Using the previous approximation results inEquation 213.EQUATION 213:I O, av,rms= I O, nomD MAXSWITCHESDuring TON, the maximum voltage drop on Q1 and Q4are that of Equation 214.EQUATION 214:andSimilarly, the maximum voltage drop on Q2 and Q3 arethat of Equation 215.EQUATION 215:V Q1, off,max= V DC, max– V Q2,on=V Q4, off,maxV DC, maxV Q3,onV Q2, off,max= V DC, max– V Q1,onand=V Q3, off,maxV DC, maxV Q4,on––Equation 216 shows the maximum voltage drop in Q2and Q3 in more general terms.EQUATION 216:V Q, off,max= V DC, max– V Q,onDIODESEquation 217 shows the voltage drop on diode D6,when Q2 and Q3 are ON.Similarly, Equation 218 shows the maximum drop onD5, when Q1 and Q4 are ON.EQUATION 217:V D6, off,max= V– S1V S2V D5, on– 2N S– + ≈ ------ ( V DC, max– 2V Q,on) + V D5,onN PEQUATION 218:,V S1V S2V D6, on– 2N S= + – ≈ ------ ( V DC, max– 2V Q,on) + V D6,onV D5 off,maxN P© 2009 Microchip Technology Inc. DS01207B-page 63

AN1207FIGURE 56:FULL-BRIDGE CONVERTER TOPOLOGY: OUTPUT CIRCUITTONTOFFTQ2 and Q3Commandt(A)TTONTOFFQ1 and Q4Commandt(B)VS1t(C)ID5t(D)ID6t(E)VLt(F)IO, avILt(G)(A) = Q2 and Q3 switch the command signal(B) = Q1 and Q4 switch the command signal(C) = Secondary voltage(D) = Diode D5 current(E) = Diode D6 current(F) = Inductor voltageG) = Output inductor voltageDS01207B-page 64© 2009 Microchip Technology Inc.

AN1207OUTPUT INDUCTORThe minimum inductor can be computed, consideringthe system at the edge of the discontinuous mode, asshown in Equation 219.EQUATION 219:I O, peakI O, av-----------------2Solving Equation 219 results in Equation 220.EQUATION 220:= =ΔI-------- O2V O≈ ---------T2L OFFOV O( 1 – D MAX)L O= -----------------------------------------2I O, av,nomF PWMOUTPUT CAPACITORThe output capacitor is selected to get the specifiedoutput ripple. The greatest contribution to voltage ripplecomes from the capacitor ESR, and the inductor currentripple, flowing through it, determines a voltagedrop.The capacitor value itself can then be computed usingEquation 221, which describes the value of the voltageripple taking into account all the components.EQUATION 221:V RIPPLED MAXESL ⋅ FI RIPPLEESR ----------------------PWM= ⎛ + + -----------------------------⎞⎝ F PWMC OD MAX⎠Neglecting ESL, since it is normally very small, resultsin Equation 222.EQUATION 222:C O=I O, rippleD MAX--------------------------------------------------------------------------------F PWM( V O, ripple– I O, rippleESR)where,V O( 1 – D MAX),= -----------------------------------L OF PWMI O ripple© 2009 Microchip Technology Inc. DS01207B-page 65

AN1207FLYBACK CONVERTERAs presented in AN1114 (see “Introduction”), FlybackConverters are widely used in applications where anisolated conversion is required, for low-power ranges(5W to 150W), and since high output voltages can bequite easily obtained because there is no inductor inthe output section.Topology Equations - Discontinuous ModeA Flyback Converter can be easily used in either Continuousor Discontinuous mode. In Discontinuousmode, the output winding current goes to zero beforethe end of the TOFF period, so that all the stored energyis transferred to the load. In Continuous mode, there issome residual energy stored in the transformer at theend of the ON and OFF periods.Both of these modes will be analyzed, starting with theDiscontinuous mode.Figure 57 shows the basic flyback circuit. The switch isdriven by a signal like the one presented in Figure 58.FIGURE 57:BASIC FLYBACK CONVERTER TOPOLOGYVD1NPNSVPVSD1COVOUTVDCVQ1Q1FIGURE 58:SWITCH Q1 COMMAND SIGNALTTONTOFFDS01207B-page 66© 2009 Microchip Technology Inc.

AN1207Q1 ON (INTERVAL 0 – TON)Figure 59 shows the topology for this circuit.Input Circuit BehaviorEquation 223 shows the voltage on the primary whenthe switch is closed.EQUATION 223:The dot end is more negative than the non-dot end.The transformer behaves as an inductor accumulatingenergy in its windings. The current flowing in theprimary is shown in Equation 224.EQUATION 224:I PV P= V DC– V Q1,onV PL P= ----- t =V DC–---------------------------------tV Q1,onL PThe increasing current, starting from zero and with apeak value reached at t = TON, is equal toEquation 225.The stored energy can be easily computed usingEquation 226.EQUATION 226:Output Circuit BehaviorThe voltage on the secondary winding is shown inEquation 227.EQUATION 227:V SE =N------ SN P1 2--L2 PI P,peak= – ( V DC– V Q1,on)where the minus sign is due to the fact that the dot endis more negative than the non-dot end terminal.Therefore, the diode D1 is reverse-biased and no currentflows into the output circuit. The output current issupplied by the output capacitor CO.EQUATION 225:V DC– V Q1,on,= ---------------------------------T ONI P peakL PFIGURE 59:FLYBACK CONVERTER TOPOLOGY: INTERVAL 0 - TONVD1NPNSVPVSD1COVOUTVDCVQ1Q1© 2009 Microchip Technology Inc. DS01207B-page 67

AN1207Q1 OFF (INTERVAL TON – (TON + TR))The circuit topology is shown in Figure 60.Input Circuit BehaviorQ1 is now open and current can no longer flow in theprimary winding. As described in AN1114 (see“Introduction”), some circuitry to dissipate the energyin the winding is required (snubber network); however,it will not be analyzed here.The voltage on the primary can be computed asEquation 228, in which VS is given by Equation 230,and the minus sign is due to the dot conversion.EQUATION 228:V POutput Circuit BehaviorAs described in AN1114 (see “Introduction”), all voltageschange sign so that in the secondary, the dot endbecomes more positive that the non-dot end and thediode starts conducting current. The current that wasflowing into the primary no longer flows because Q1 isnow open, and transfers to the secondary as an initialcurrent equal to Equation 229 with a down slope, sothat it reaches zero at time TON + TR.N P= –------V SN SEQUATION 229:N PI Speak ,N SThe voltage at the secondary is shown in Equation 230.EQUATION 230:Q1 OFF (INTERVAL (TON +TR) - T)As previously stated, at time TON + TR, the current in thesecondary has reached zero. To keep the system workingin Discontinuous mode, some time (TF) must beadded, as shown in Equation 232.EQUATION 231:------I P peak------ V DC– V Q1,on= = ---------------------------------T ONN P,N SV S= V O+ V D1,onT = T ON+ T R+ T FThis is because the TON interval depends on the inputvoltage VDC and the output load and if, for instance,VDC decreases or the output current increases, the ONduration must be longer. TF will be consequentlyreduced, but will allow the system to be discontinuous.L PFIGURE 60:FLYBACK CONVERTER TOPOLOGY: INTERVAL TON - TRVD1NPNSVPVSD1COVOUTVDCVQ1Q1DS01207B-page 68© 2009 Microchip Technology Inc.

AN1207Design Equations and ComponentSelectionINPUT/OUTPUT RELATIONSHIP AND DUTYCYCLEThe input/output relationship is computed consideringthe power flow from input to output.From Equation 226 the power stored in the primary canbe computed, as shown in Equation 232.EQUATION 232:EP = -- =TThe relationship between input and output power isshown in Equation 233.EQUATION 233:By combining Equation 232 and Equation 233, the outputvoltage as a function of the input voltage can bedetermined, as shown in Equation 234.EQUATION 234:Since the TON interval is a function of the input voltageVDC, the maximum TON (TON, max) corresponds to theminimum input voltage (VDC, min). Using these values,(VDC, min is a design spec and TON, max is usually setto some value so that TON, max + TR =0.8T),Equation 234 can be revised, as shown inEquation 235.EQUATION 235:( V DC– V Q1,on) 2 2T ON---------------------------------------------------2TL PP OUT=ηP INηRFV O= V DCT PWMON----------------------2L PEQUATION 236:V DC, minV Q1,onI P, peak=L PEQUATION 237:N PI S, speak=N STRANSFORMER WINDINGS TURN RATIOTo determine the ratio (NP/NS) we can have a look atthe maximum voltage the Q1 MOSFET has to be ableto sustain.Considering Figure 57, the maximum voltage on theswitch is equal to that of Equation 238.EQUATION 238:The primary voltage, VP, is calculated usingEquation 228 and Equation 230, which results inEquation 239.EQUATION 239:If a MOSFET is selected with a sufficiently high voltagerating, VQ1, off is considered as a datum so that inEquation 239, the only unknown value is (NP/NS);therefore, NP/NS is equal to that of Equation 240.EQUATION 240:–-------------------------------------------T ON,max------ V DC, min– V Q1,on-------------------------------------------T ON,maxL PV Q1, off,max= V DC, max– V PN PV Q1, off,max= V DC, max+N SN------ PN S=------ ( V O+ V D1,on)V Q1, off,max– V------------------------------------------------------- DC,max( V O+ V D1,on)V O=V DC, minT ON maxηRF PWM,----------------------2L PTwo other equations, primary peak current(Equation 225) and secondary peak current(Equation 229), can be revised to take into account theVDC, min and TON, max relationship, as shown inEquation 236 and Equation 237, respectively.© 2009 Microchip Technology Inc. DS01207B-page 69

AN1207MAXIMUM ALLOWABLE TONTo determine the maximum TON, the fact that the coreshould never saturate is considered. This means thevoltage-time interval product during energy storagemust equal the voltage-time interval product during thedelivery of energy to the load. In simpler terms, area A1must equal area A2, as shown in Figure 61.Considering that TON, max + TR = βT with β < 1, asshown in Equation 241, which after computation,results in Equation 242.EQUATION 241:T ON max,+ T R= βTEQUATION 242:------ ( V O+ V D1,on)β---------------------------------------------------------------------------------------------------------------------------N P( ) + ------⎝⎛ ⎠⎞ ( VO + V D1 ,) F on PWMT ON, max=N SN PV Dc, min– V Q1,onN STRANSFORMER PRIMARYThe value of the transformer primary inductance can beeasily computed using Equation 235, replacingTON, max with the computed value from Equation 242,where the design specification, POUT, max = VO 2 /RO,results in that of Equation 243.EQUATION 243:L P2 2V DC,minT ON,maxRηF----------------------------------------------------------------- PWM22V O= =2 2V DC,minT ON,maxηF------------------------------------------------------------- PWM2P OUT,maxDS01207B-page 70© 2009 Microchip Technology Inc.

AN1207FIGURE 61:FLYBACK CONVERTER TOPOLOGY WAVEFORMS: DISCONTINUOUS OPERATIONTT = TON + TRTON TR TFQ1 commandt(A)VDC - VQ1, onA1VPt(B)(NP/NS)(VO + VD1, on)IP, peakIPt(C)VO + VD1, onA2t(D)t(E)(A) = Command voltage on Q1 MOSFET gate(B) = Voltage on the primary winding of the transformer(C) = Current flowing in the primary winding of the transformer(D) = Voltage on the secondary winding of the transformer(E) = Current flowing in the secondary winding of the transformer© 2009 Microchip Technology Inc. DS01207B-page 71

AN1207TRANSFORMER: PRIMARY, WIRE SIZEAs can be seen in Figure 61(C), the current in the primaryhas a triangular shape, with a peak at t = TON.Based on this, the rms value can be computed asshown in Equation 244.EQUATION 244:I P, peakI PRIMARY, rms=3---------------- T ON max,F PWMIn Equation 244, IP, peak is calculated fromEquation 225, and TON, max, is calculated fromEquation 242, which results in that of Equation 245.EQUATION 245:–-------------------------------------------T ON,maxV DC, minV Q1,onI P, peak=L PTRANSFORMER: SECONDARY, WIRE SIZEFrom Figure 61(E), the current in the secondarysimilarly has a triangular shape. The rms value is thencalculated using Equation 246.EQUATION 246:I Speak ,I SECONDARY, rms=3N---------------- PT RF PWM------ I P,peak= ---------------- T RF PWM3N SOUTPUT DIODEThe current flowing through the output diode is thesame current flowing into the secondary, with its peakvalue computed in Equation 228. The average currentcan be computed as shown in Equation 247.EQUATION 247:1 T RI D1, av= --I S, peak-----2TOUTPUT CAPACITORThe output capacitor can be computed considering thatit has to supply the whole current to the load duringTON. The criteria to be used is that the voltage droopshould be less than the acceptable output voltage ripple.Since the voltage droop is equal to Equation 249,the capacitor value can be computed as shown inEquation 250.EQUATION 249:The maximum reverse voltage on the diode, during TONcan be computed as shown in Equation 248.V DROOP=I O, maxT------------------------------------- ON,maxC OEQUATION 248:N SV Q1, off,max= ------N P– ( V DC, max– V Q1,on)–V OEQUATION 250:C O=I O, maxT-------------------------------------------------------ON,maxV ACCEPTABLE_RIPPLEDS01207B-page 72© 2009 Microchip Technology Inc.

AN1207Topology Equations – Continuous ModeIn Continuous mode applications, the basic circuit doesnot change (refer to Figure 57); however, the essentialdifference is that the current (both in the primary windingand the secondary winding) will not start andreaches zero during the PWM period, T. This meansthat some energy is still stored in the system when thePWM period is over.The period T is now made up of TON and TOFF only. Thebasic topology equations are exactly the same asbefore, so they are presented without repeating all ofthe previous explanations.Q1 ON (INTERVAL 0 – T ON )Input Circuit BehaviorEquation 251 shows the voltage on the primary winding.EQUATION 251:The current in the primary is shown in Equation 252.EQUATION 252:Equation 253 shows the peak current at the end of TON.EQUATION 253:I P peakOutput Circuit BehaviorThe voltage on the secondary is shown inEquation 254.EQUATION 254:V P= V DC– V Q1,onV DC– V Q1,onI P= ---------------------------------tL PV DC– V Q1,on,= ---------------------------------T ONL POutput Circuit BehaviorEquation 256 shows the voltage on the transformersecondary winding.EQUATION 256:The initial current (reflected from the primary), is shownin Equation 257.EQUATION 257:N PI Speak ,=N SDesign Equations and ComponentSelectionINPUT/OUTPUT RELATIONSHIP AND DUTYCYCLELooking at Figure 62(B), the areas A1 and A2 must beequal so that the initial and final points on the transformercore hysteresis curve coincide, as shown inEquation 258.EQUATION 258:V S= V O– V D1,onN P------I P, peak------ V DC– V Q1,on= ---------------------------------T ONN P( V DC– V Q( 1,on))T ON= ------ ( V O+ V D( 1,on))T OFF⇒V OD =N SN PN SThe maximum TON/T value, can be computed fromEquation 258 to occur with VDC, min (where NP/NS iscomputed in Equation 260), which results inEquation 259.N S------D= ( V DC– V Q1,on)------------1 – DT--------- ONTL PV S=N S–------( V DC– V Q1,on)N PEQUATION 259:Q1 OFF (INTERVAL T ON – T)Input Circuit BehaviorThe voltage on the primary is shown in Equation 255.T-------------------- ON, maxTN P------ ( VN O+ V D1,on)S= --------------------------------------------------------------------------------------------------N P( V DC, min– V Q1,on) + ------ ( V O+ V D1,on)N SEQUATION 255:V P=N P–------V SN S© 2009 Microchip Technology Inc. DS01207B-page 73

AN1207FIGURE 62:FLYBACK CONVERTER TOPOLOGY WAVEFORMS: CONTINUOUS OPERATIONTONTOFFQ1 commandt(A)VDC - VQ1, ONA1VPt(B)(NP/NS)(VO - VD1, ON)A2IP, peakIP, avIPt(C)VO - VD1, ONVSt(D)(NS/NP)(VDC - VQ1, ON)IS, peakISt(E)(A) = Command voltage on Q1 MOSFET gate(B) = Voltage on the primary winding of the transformer(C) = Current flowing in the primary winding of the transformer(D) = Voltage on the secondary winding of the transformer(E) = Current flowing in the secondary winding of the transformerDS01207B-page 74© 2009 Microchip Technology Inc.

AN1207TRANSFORMER WINDINGS TURN RATIOTo determine the ratio (NP/NS), the maximum voltagethe Q1 MOSFET can sustain must be calculated, asshown in Equation 260.EQUATION 260:TRANSFORMER: SECONDARY, WIRE SIZEThe output average current (IO, av) must be determined.To do so, the output power (which is one of thedesign data) is considered, as shown in Equation 263.EQUATION 263:N------ PN S=V Q1, off,max– V------------------------------------------------------- DC,max( V O+ V D1,on)-----------------------------------------------------------------------– ⎞⎝⎠I O, av=P OUT( V O+ V D1,on) ⎛1T-------------------- ON, maxTTRANSFORMER: PRIMARY, WIRE SIZEConsidering a desired output power PO, as shown inEquation 261, the rms value can be computed replacingthe real current (RAM on a step) with a constantvalue, equal to IP, av. The rms value is then equal toEquation 262.EQUATION 261:P OUTηP INηI P, av( V DC– V Q1,on) T ON,max= =-------------------- ⇒T-----------------------------------------------------( ) T ON---------TI P, av=P OUTη V DC– V Q1,onCorrespondingly the rms value is that of Equation 264.EQUATION 264:I O, rms= I O, avD MAXTRANSFORMER: PRIMARY INDUCTANCEThe minimum LP inductance can be easily computed ifthe system at the edge of the Discontinuous mode isconsidered. This means that the IP, peak is exactly onehalf of the increment in primary current during TON.Therefore, the minimum average input current is that ofEquation 265.EQUATION 262:I P, rms= I P, avD MAXEQUATION 265:= --------------------------------------------------------------------------η( V DC, min– V Q1,on) T =ON,max--------------------TP OUTI P, av,minΔI-------- P2=V DC, min– V Q1,on( )------------------------------------------------ T2L ON,maxPSolving LP, results in Equation 266.EQUATION 266:L P=η( V DC, min– V Q1,on)( V DC, min– V D1,on)T ON,max2F PWMOUTPUT CAPACITORThe output capacitor is computed as in theDiscontinuous mode, as shown in Equation 267.EQUATION 267:C O=I O, maxT-------------------------------------------------------ONmax ( , )V ACCEPTABLE_RIPPLE© 2009 Microchip Technology Inc. DS01207B-page 75

AN1207VOLTAGE AND CURRENTTOPOLOGIESIn this section, control loops and voltage and currentmodes are analyzed. A Buck Converter is used, butthese techniques are valid for any topology.In all topologies, it has been seen that an input/outputrelationship can be easily obtained. So long as thedesired input and output voltages are known, all thatremains is to compute the PWM duty cycle. In a perfectworld, this would be more than enough.Unfortunately, in the real world, things behavedifferently. The input voltage can change, the load canvary (i.e., switching the output load On and Off),components have their tolerances, aging andtemperature drift and, of course, noise is alwayspresent. As a result, performances can differ fromexpectations.To keep the behavior of the system under control duringunexpected situations, a “control loop” (hardwareand/or firmware) must be added to perform the operationof “controlling” the output voltage. Control loopsallow the design of a circuit where the output voltagewill vary as little as possible when any environmentalcondition changes. Moreover, in some cases, controlloops help in preventing dangerous operational situations.Current control loops can prevent flux walking inthe transformers.In the following sections, the voltage and currentmodes of operation will be described for each topology,keeping the following two basic questions in mind:1. What happens to the system output voltagewhen the input voltage suddenly changes?2. What happens to the output voltage when theload changes?Voltage LoopFigure 63 presents the Buck Converter previously studiedin detail, with some additional circuitry. A couple ofseries resistors (R1 and R2) connected to the outputtake a reduced amplitude copy (VFB) of VOUT. This voltageis compared in the error amplifier (EA) with a referencevoltage (VREF – the voltage value desired at theoutput). The output signal (VX) is used to trim the dutycycle of the PWM signal that drives the switch.To understand how the PWM block works, thetechnique that is commonly used in the analogimplementation of such systems will be used initially.This does not mean that this is the only possibleimplementation. Later, how to digitally implement thesame features with a dsPIC ® DSC device is discussed.The analog version is instead quite easy and intuitiveand allows for a simple explanation of how things work.The PWM block can be replaced by a comparator thatcompares the VX voltage to a sawtooth signal, generatedby a local oscillator (see Figure 64). Its frequencyis the PWM frequency.FIGURE 63:BUCK CONVERTER - BASIC VOLTAGE LOOPLOR1COR0R2PWMVXEAVFBVREFDS01207B-page 76© 2009 Microchip Technology Inc.

AN1207FIGURE 64:BUCK CONVERTER - BASIC ANALOG VOLTAGE LOOPLOR1COR0R2VCTRLVX -EA+VFBVREFNote: VX = VREF – VFBVSTSawtoothOscillatorHere is how the system works. The VFB voltage, representingthe current output voltage, is subtracted in theerror amplifier EA from the reference voltage VREF. So,at least for now, the function of the EA block is just toperform a subtraction. Signal VX represents the errorbetween the desired voltage and the “real” voltage thesystem is generating at that instant in time. The VX signalat Steady state, has a very slow moving averagevalue. In the comparator, this signal is compared to thelocally generated sawtooth, as shown in Figure 65,which results in VCTRL = 1, if VST < VX, or VCTRL = 0, ifVST > VX.FIGURE 65:CONTROL VOLTAGE (VCTRL) GENERATED BY COMPARISON BETWEEN ERRORVOLTAGE (VX) AND THE SAWTOOTH WAVEFORMVSTVOUT decreaseVXVOUT increaseVCTRLNote: VX = VREF – VFBSince VCTRL is the PWM signal used to drive theswitches, and is based on the value of VX, the dutycycle will either be small or large.The operation in the EA is such that when the outputvoltage increases, the VX voltage decreases, so thatthe PWM duty cycle is reduced and vice versa. Thefalling edge of VCTRL moves according to the positionof VX relative to VST.© 2009 Microchip Technology Inc. DS01207B-page 77

AN1207LINE REGULATIONThe question now is: how does this system react whenthe input voltage changes? In answering this question,consider that the ultimate goal is to keep the output asstable as possible against any variation of the input.In addition, a couple of basic equations, derived previouslymust be taken into consideration, which describethe behavior of the Buck Converter.Equation 268 shows the current in the inductor duringTON, While during TOFF the current is equal toEquation 269.EQUATION 268:I L, on() tEQUATION 269:I L, off() t( )= ---------------------------------- tV DC– V OUTL O=V OUT–------------- tL OAt Steady state, the current value at t = 0 equals thecurrent value at t = T. This is represented in Figure 66,in the event of a Continuous operating mode. The outputaverage current (IO, av) (see Equation 270) is alsoplotted.EQUATION 270:I L, peak– I L( 0),= I L( 0)+ -----------------------------------2I O avSo, what happens if the input voltage VDC increases?Since the up-slope of the inductor current isproportional to VDC, its slope will increase during TON.With some delay, due to the LC low-pass filter, theoutput voltage will change (increase), and with someadditional delay introduced by the EA, the VX signal willdecrease. Therefore, the duty cycle of VCTRL will thenbe smaller (see Figure 65). This will reduce the TONtime, reducing as a consequence VOUT and so, aftersome time, the output will again be at the nominalvalue, with a shorter duty cycle. Note that only theslope of IL during TON changes. The slope during TOFF,in the new Steady state condition, must be equal to theoriginal one, since the system is keeping VOUTconstant.Figure 67 presents the inductor current before thechange in VDC (dashed line) and after the transientshave settled down in a new Steady state (solid line).The initial and final current values (at t = 0 and t = T)are lower, but at the same time the peak (point B) ishigher. The average current (IO, av) has not changedas it was expected since the average output voltagehas not changed. Of course, point B corresponds to ashorter on period (TON).FIGURE 66:INDUCTOR CURRENT IN CONTINUOUS MODEILIL, peakIO, avIL(O) =IL(T)O TON TtDS01207B-page 78© 2009 Microchip Technology Inc.

AN1207FIGURE 67:VOLTAGE MODE CONTROL - LINE REGULATIONILBAIO, avInitialFinalTONTONTt© 2009 Microchip Technology Inc. DS01207B-page 79

AN1207LOAD REGULATIONThe question now is: what happens if the loadchanges?For example, if the RO value changes by diminishing,at the very beginning (because of delays in the system)the output current will remain as before. This meansthat the output voltage will decrease only slightly. As aconsequence, referring again to Figure 64 andFigure 65, the VX signal will be higher and the dutycycle will increase. The behavior of the system can beanalyzed using Figure 68, which again represents theinductor currents, before (dashed line) and after (solidline) the load change. This time both slopes, during TONand TOFF, will remain the same, since the input voltagehas not changed and the output voltage is keptconstant by the loop itself.At the beginning, since VX increases, the duty cycle willincrease, moving from the original point A to point B.This means that the current at the end of the PWMperiod (point M, current at t = T) will be a bit larger thanthe initial current (point H, current at t = 0). The effect isthat at the end of each PWM period, the current step isgreater than zero, as shown in Equation 271.EQUATION 271:ΔI L() t = I L( T) – I L( 0)When the transient ends, the loop has managed tobring the output voltage VOUT back to its nominal valueand consequently, the duty cycle is back to its initialvalue (there was no change in input voltage VDC). Thismeans that, in Figure 68, point B has moved to point C,in the new Steady state. The output average currenthas correspondingly increased from IO, av, initial toIO, av, final, as it was supposed to do since the load ROhas diminished.FIGURE 68:VOLTAGE MODE CONTROL - LOAD REGULATIONCBAIO, av, finalIO, av, initialHMΔIL(T)TONTtDS01207B-page 80© 2009 Microchip Technology Inc.

AN1207ADVANTAGES AND DISADVANTAGES OFVOLTAGE MODEAs is clearly seen from the previous explanation, theimplementation of a voltage mode control is quitestraightforward. The mechanisms of line and loadregulation are also quite easy to understand. This iscertainly one of the main advantages of this approach.Moreover, large amplitude signals are usually beingdealt with, which is a benefit because of their goodnoise margin.The key disadvantage of this mode is the delay, whichis always added in reacting to any change of operatingconditions. A change in VDC is only detected becauseof its influence on the output voltage, so that from theoriginal event (change in VDC), detection makes it necessaryto wait for the group delay of the low-pass filter.Moreover, once the change in output is detected, anadditional delay is introduced by the EA. All of thesedelays must be taken into account; otherwise, a systemis built that is not functional.A change in the load is immediately detected, butagain, there is a delay introduced by the EA before thecountermeasure can be effective on the switch timing.Current ModeThe current mode has been introduced to solve the disadvantagesof the voltage control and, specifically, toreduce the reaction time of the system.It also has some very specific advantages when needingto keep the current flowing into an inductor/transformerwinding under control. A typical exampleapplication where the current mode is efficiently used isa PFC, which is a circuit whose task is to force the currentdrawn from the AC voltage source to be sinusoidal.In this case, the current mode control directly operateson the variable (current) of interest.As seen in Figure 69, a current mode implementationhas in reality two loops: one external controlling theoutput voltage (like the one studied in the previousparagraph) and the second one (internal) controllingthe inductor current. The basic idea of the current modeis to directly monitor the quantity that is more directlyresponsible for the power conversion. Moreover, controllingthe current allows to have a much fasterresponse time.Referring to Figure 69, the EA as before, monitors theoutput voltage. Its output is used as a reference signalto a second amplifier that compares the peak currentflowing into the inductor to the reference signal from theprevious stage.Remember that when switch Q is closed, the inductorcurrent has a positive slope waveform (Figure 70). Atthe beginning of the PWM period (t0), the PWM outputis set active and the inductor current continues to growuntil the current reaches the value of VX. When theymatch (t0 + TON), the PWM signal is reset and remainslow until the next PWM period starts. This systemkeeps the peak inductor current under control.However, this is not the only possible approach, as willbe seen later.FIGURE 69:CURRENT MODE CONTROL LOOPQImeasPWMCAVXVFBVREF© 2009 Microchip Technology Inc. DS01207B-page 81

AN1207FIGURE 70:INDUCTOR CURRENTVXt0 t0 + TON TThe key point is that in the Buck Converter, the inductorcurrent is also the output current, so that controlling ithas the direct control of the quantity of relevance(VOUT). As previously seen in other systems, forinstance, in a PFC, the inductor current is the inputcurrent and it should be shaped in a sinusoidal way.In this configuration, the externally generated sawtoothsignal that was used in the voltage mode control isreplaced by the inductor current signal and its peakvalue is controlled (limited).The system is relatively simple but also has a couple ofdrawbacks:• It is preferred to be able to control the averageoutput current, not the peak current (this isbecause the output voltage is proportional to theaverage current, not the peak current)• There are some stability issuesLINE REGULATIONWhat happens when, being in Steady state, the inputvoltage changes? How does the system respond?This behavior can be best understood by looking atFigure 71 (dashed lines represent the original Steadystate). For example, as soon as VDC changes byincreasing, the slope of the inductor current changes(see Equation 268). In this case it will increase. Meanwhile,the output has not yet changed, because of thedelay of the output LOCO filter. Consequently, VFB hasnot changed and VX is the same as before. The loop isstill imposing the same inductor peak current as before.This means that the up-slope current signal will crossthe VX signal before, in point B compared to the Steadystate point A (the transient behavior of the inductor currentis shown with line from point L to point B). The dutycycle is reduced as it should be because of theincreased input voltage. The final, new Steady statecondition is point C, still on the VX line (the peak currentis always the same), having steeper up-slope and thesame down-slope. The important thing is that the reactionto the input voltage change is immediate, withouthaving to wait for the change to propagate along theloop. In other words, the system response is muchfaster.FIGURE 71:PEAK CURRENT MODE CONTROL - LINE REGULATIONB C AVXOIO, av, initialIO, av, finalLHMKTON, initialTON, finalTON during transientTtDS01207B-page 82© 2009 Microchip Technology Inc.

AN1207PROBLEMSAs seen in Figure 71, while the input voltage regulationworks fine (an increase in VDC brings about a reductionof the duty cycle), there is a drawback as seen inEquation 272. This is due to the fact that the peakvoltage is being kept constant, while the output voltageVOUT is proportional to the average inductor voltage.EQUATION 272:V OUT av,= R OI O,avHowever, as observed in Figure 71, the new conditionis such that the inductor current initial and final values(points H and K) are lower than before (L and M). Thismeans that the final average inductor (output) currentis lower, as shown in Equation 273.EQUATION 273:I O, av,final< I O,av,initialA lower current will develop a lower output voltage,which will be detected by the external voltage loop. Inturn, it will try to increase the average (and peak)current. But the internal loop tries to keep the peakcurrent constant. An oscillatory effect takes place andcontinues for some time.Another subtle problem of the peak current mode isthat the system is unstable for duty cycles greaterthan 0.5, which can be seen in Figure 72 andFigure 73.FIGURE 72: PEAK CURRENT MODE CONTROL - D > 0.5D > 0.5ΔIIΔIFΔIF > ΔIIFIGURE 73:CURRENT MODE CONTROL - SLOPE COMPENSATIONDown slopeDown slopeVXInductor current© 2009 Microchip Technology Inc. DS01207B-page 83

AN1207As seen in Figure 72 when D < 0.5, at steady state, iffor any reason there is a pertibation in the inductorcurrent, at the end of the PWM period, the amplitude ofthe pertibation is reduced (ΔIF < ΔII), so that after anumber of PWM cycles, the system will be back at theinitial condition. On the contrary, if the duty cycle isgreater than 0.5 (Figure 73), the same currentpertibation will be larger at the end of the period and willgrow indefinitely, giving rise to an oscillatory behavior(ΔIF > ΔII).Without going into too many details, both problems canbe easily corrected replacing the constant VX peak currentlimit with a down slope signal that equals VX at thebeginning of each period, and which has a down slopeproportional to half the current slope during TOFF(Figure 73).Load CompensationWhat happens when the output load changes?For example, if the output load changes by decreasing,the output voltage will momentarily decrease and consequentlythe VX signal will be higher to compensatefor it (see Figure 74).The up slope signal will then last longer and will crossVX at point B, instead of the original point A, and theduty cycle will correspondingly increase. This willcause the inductor current level to be higher at the endof the PWM period compared to its value at the beginning(ΔIF, is extremely exaggerated in Figure 74 forclarity). This unbalance will remain while the averagecurrent increases to the new equilibrium value. At thispoint, the duty cycle is back to its initial value (nochanges in input voltage VDC) and the system hasreached a new steady state.FIGURE 74:PEAK CURRENT MODE CONTROL - LOAD COMPENSATIONABVX during transientVX at steady stateΔIFOTON during transientTTON at steady stateDS01207B-page 84© 2009 Microchip Technology Inc.

AN1207Other Current Mode TechniquesThe current mode previously described with somedetail is not the only one available. The most obvioustechnique is one where the loop keeps the average (notthe peak) output current constant. This is good, sincethe output voltage is proportional to the average outputcurrent.In analog, the circuitry is a bit more complex sincesome kind of low-pass filter must be added to thecurrent loop error amplifier. On the contrary, from adigital point of view, the technique is very easy sincethe average value of the current can be directlysampled and converted by the ADC if the samplingtrigger is at half the period of the duty cycle. A specialregister in the dsPIC DSC device allows the conversionto start operation exactly at this point (see Figure 75).A second possibility is to implement the so-called hystereticcontrol, where the current value can changebetween two values, which can be either fixed ordynamically computed by the dsPIC DSC device itself.In this case, the internal comparators and their thresholdset by DACs allow implement of the system withoutany intervention from the CPU (see Figure 76).As seen in Figure 76, as soon as the decreasinginductor current reaches threshold one, the current limitevent in the dsPIC DSC device takes place, andassociated with it is the forcing high of the pin. As aconsequence, current starts rising. As soon as itreaches the second threshold, the fault event takesplace and the output pin is reset, current decreases,and so on. The frequency of the generated PWM is notconstant, but it will change as a function of line and load(remember that the up slope is proportional to VIN andthe down slope is proportional to VOUT).FIGURE 75:ADC TRIGGER GENERATED BY PWM PERIPHERALPWMSignalInductorCurrentTrigger to ADC to start conversiontSEVTCMP Register=16 16PWM Time BaseCounterFIGURE 76:HYSTERETIC CONTROL IMPLEMENTATION WITH A dsPIC ® DSC DEVICEdsPIC ® DSCDAC1TH1CL SetOutputPWMxHCPUPWMIPPDAC2TH2FaultResetPWMxLTH2Inductor CurrentTH1© 2009 Microchip Technology Inc. DS01207B-page 85

AN1207The internal comparators can also be used to implementa “constant on” time or a “constant off” time (seeFigure 77 and Figure 78), where the match betweenthe increasing inductor current and a preset threshold(DAC output) resets the PWM timer that controls thePWM period. The two control modes are essentially thesame, the only difference being that the direct orinverted PWM output is considered.FIGURE 77:“CONSTANT ON” TIME WAVEFORMExternal ResetNominal PeriodiPWM Time Base CounterTONTONFIGURE 78:“CONSTANT OFF” TIME WAVEFORMExternal ResetNominal PeriodiPWM Time Base CounterTOFFTOFFDS01207B-page 86© 2009 Microchip Technology Inc.

AN1207Control TheoryUp to this point, feedback loops have been consideredwhere the output VOUT is compared to a referencevalue, and the error signal is used to change some specificfeature (i.e., the duty cycle) of the power modulator.This is a closed loop system and must be analyzedwith control theory tools.The problem here is that the system could becomeunstable if either the current or voltage loop is used. Inthe general circuit, like the one in Figure 63 andFigure 69, the behavior of any block, excluding EA andCA can be known or computed. The design challengeis then to select the EA (and CA) transfer function to besure the system is stable.Before analyzing the Buck Converter circuit from a controltheory perspective, some basic relationships mustbe formulated.FEEDBACK LOOPSFigure 79 presents a general control loop where G(s)and H(s) are the transfer functions of the two blocks(Laplace transforms of the impulse responses). x(t) isthe input signal to the system; y(t) is the output; y(t) isalso fed back to the input through H(s) block, whoseoutput, r(t) is subtracted from the input x(t) to form theerror signal e(t).Equation 276 shows the product of the two terms, G(s)and H(s), which is called open loop gain (GOL(s)).EQUATION 276:Figure 80 represents G(s), H(s), GOL(s) and GCL(s).Remember that the plot is in log scale, so that multiplicationscorrespond to sums and divisions correspondto subtractions.FIGURE 80:G OL( s) = Gs ( )Hs ( )CONTROL LOOPFUNCTIONS|G(s)||GOL(s)|fCO|1/H(s)|f|GCL(s)|FIGURE 79:CONTROL LOOPSome mathematics to understand the plot are providedin Equation 277.+-x(t)e(t)+ G(s)y(t)r(t)H(s)With computation, as shown by Equation 274, theinput/output relationship can be derived, which is calledclosed loop gain (GCL(s)).EQUATION 274:G CL( s)= --------------------------------Gs ( )1 + Gs ( )Hs ( )GCL(s) can be simplified using Equation 275.EQUATION 275:G CL( s)⎧ 1⎪----------- if Gs ( ) >>1= ⎨Hs( )⎪⎩Gs ( ) if Gs ( )

AN1207Solving Equation 278 results in Equation 279.EQUATION 279:The phase of G( s)Hs( ) must be ≠ 180°where G( s)Hs( ) = 1Referring to Figure 80, it is recognized that the pointwhere |GOL(s)| = |G(s)H(s)| = 1 is fCO (crossover frequency).The phase at this frequency must be differentfrom 180°. To be on the safe side, a phase of about130°-140° is requested, or correspondingly a phasemargin = (180° - phase at fCO) ≥ 45°.With some simplifications, the criteria of stability can bestated as:• The slope of GOL(s) at fCO must be -20 dB/decadeand,• The phase margin at fCO must be at least 45°.These are only sufficient conditions for the stability, butare widely used because of their simplicity.The meaning of the second criteria should be clearfrom the previous discussion. The first criteria can beinterpreted this way.By looking at the GOL(s) transfer function, it is observedthat it is a ratio of polynomials. With some effort (at thispoint it does not really matter how difficult it can be), theGOL(s) numerator and denominator can be transformedinto the product of first order terms (eventuallycomplex numbers), as shown in Equation 280.EQUATION 280:G OL( s)=N∏k = 1M( s – )z k---------------------------∏l = 1( s – )p lEach term of the numerator is a zero, each term at thedenominator is a pole. In normal conditions, like thoseencountered in power supply units, each zerocontributes to the open loop gain phase with a +π/2phase contribution, while each pole contributes with a–π/2 phase contribution. From the point of view of theloop gain, each zero gives place to a change in theslope of the gain itself of +20 dB/decade, while a polegives a -20 dB/decade slope change. Therefore, theslope the GOL(s) criteria previously mentioned can beinterpreted as in the nearby of the crossover frequency(fCO), the total contribution to the loop gain is similar towhat a single pole system would provide.POWER CONVERTER AND CONTROLTHEORYNow that you have a rough idea of the meaning of stabilityand the criteria to determine if a system is stable,refer back to the Buck Converter with a voltage modecontrol loop (Figure 63). It is imperative to match theconverter functions to the general control theory blockdiagram and determine the transfer functions.Therefore, Figure 63 can be redrawn as Figure 81,where G(s), the input to output transfer function, ismade up of three blocks:• GEA(s) is the error amplifier transfer function• GM(s) is the transfer function of the PWMgenerator• GLP(s) is the output low-pass filter transferfunction.H(s), the transfer function from the output to the input isabsent, or better: H(s) = 1.FIGURE 81:BUCK CONVERTER VOLTAGE MODE LOOPVREFGEA(s)GM(s)GLP(s)DS01207B-page 88© 2009 Microchip Technology Inc.

AN1207The GM(s) transfer function is probably not immediatelyintuitive. But think of it this way: if the input signal is aDC value with a small amplitude sinusoidal waveformripple superimposed, the output will be a PWM signalwhose duty cycle value follows the same sinusoidal lawaround the Steady state value. Simplistically, the input/output relationship is the ratio between the output dutycycle range and the input sinusoidal amplitude and thefrequency is preserved. There are a few differenttechniques that can be used to mathematicallydetermine the I/O relationship. Without going into suchdetails the important thing is that as soon as thetopology and the power system have been decided,GM(s) can be computed.GLP(s) is somehow easier, and can be computed analytically,considering the low-pass filter in Figure 82,where the output capacitor ESR has also been takeninto account.FIGURE 82:BUCK CONVERTEROUTPUT STAGEFIGURE 84:|GEA(s)|ERROR AMPLIFIERTRANSFER FUNCTIONReferring to the previous equations, GOL(s) =G(s)H(s) = GEA(s)GM(s)GLP(s), being H(s) = 1.Working in dB, results in Equation 281.EQUATION 281:fzfpfVILVOUTG OL( s) dB= G EA( s) dB+ G M( s) dB+ G LP( s) dBCOknownR0knownESRunknownunknownAt this point, GM(s) and GLP(s) are known: the designeffort consists in finding a function GEA(s) that makesthe system stable according to the definition previouslygiven. In an analog design, this translates into thecomputation of a few passive components in standardcompensating networks, where an op amp is used.One such circuit is shown in Figure 83 and its transferfunction is shown in Figure 84.FIGURE 83:ERROR AMPLIFIERNETWORKC2The following details the preferred gain even if |GOL(s)|is not known:• The lower the frequency, the higher the gainshould be; this is because a very high gain at lowfrequencies gives place to small Steady stateerrors• The higher the frequency, the smaller the gainshould be to reduce the effects of high frequencynoise• In between frequencies it would be best to have afairly constant gainIt can be concluded, the known and desired |GOL(s)|value can be stated, resulting in Equation 282.EQUATION 282:C1R2G EA( s) dB= G OL( s) dB– G M( s) dB– G LP( s) dBVINR1GEA(s)VOUTIn an analog implementation, a graphical solution caneasily be found. In a less systematic approach, differentcapacitor values can be tested in the circuit ofFigure 83 and Figure 84 until a satisfactory solution isfound.© 2009 Microchip Technology Inc. DS01207B-page 89

AN1207Digital SolutionsUntil now, only the analog solutions (how the voltageand current mode loops can be implemented in analog)have been considered. This is because, for beginners,it is easier to understand the basic concepts in the analogdomain first and then convert them to the digitalworld. On the contrary, many experienced converterdesigners have great experience in analog design andthe presented material is the foundation upon which thedigital approach is built on.Of course, in a digital solution the passive powercomponents will be used; what changes is the way thePWM is generated and how the feedback loop isimplemented.An overview of Microchip Switch Mode Power Supplydevices follows, which provides an understanding oftheir architecture and the features they provide, whichcan be used to implement a Switch Mode Power Supply.SWITCH MODE POWER SUPPLY (SMPS)dsPIC DSC DEVICESMicrochip’s dsPIC DSC SMPS devices have beencreated specifically to aid designers with theimplementation of digital switching systems. Thesedevices are 16-bit processors based on the wellestablished dsPIC30F and dsPIC33F family of devices,with three main building blocks:• 16-bit MCU• Digital Signal Processor core• Intelligent Power Peripheral (IPP)IPP is a superset of three peripherals: a PWM generator,a high-speed 10-bit analog-to-digital converter(ADC), and a high-speed comparator. Nothing newcompared to many other processors? On the contrary,a lot of new features! The key points are:• High performance of the peripherals• High degree of interconnection between the threementioned peripherals, that cooperate to the generationand control of the PWM output waveformwithout the direct intervention of the CPUThe PWM signals (up to four complimentary outputs)can have the same frequency, or each one can operateindependently with a duty cycle resolution as low as1.05 ns. The PWM can operate in nine different modes:• Standard edge-aligned PWM• Complementary PWM• Push-pull PWM• Multi-phase PWM• Variable phase PWM• Fixed off-time PWM• Current reset PWM• Current-limit PWM• Independent time base PWMThe PWM can generate a set of triggers that will startthe ADC operation, fault signals can stop the PWMoperation, currents greater than a defined threshold inthe internal comparators can inhibit the PWM outputs,and the PWM period counter can be reset by externalsignals to implement constant-off/-on outputs.The high-speed 10-bit ADC can sample up to fivesignals at the same time and will always convert twoinput channels at a time (usually one current and onevoltage). Multiple triggers can start the converteroperation:• Individual software trigger• Global software trigger• PWM Special Event Trigger• PWM generators trigger• Timer1 or Timer2 period match• PWM generators current-limit ADC trigger• PWM generators Fault ADC triggerThe comparators can be used to detect overcurrent, oras in some current mode loops, be used to detect whenthe inductor current has reached a preset value.While the IPP takes care of the greater part of the generationand management of the PWM, ADC, and comparatorsignals, the CPU and its DSP engine haveplenty of time to perform the computations required toclose the control loop in a digital solution.The 16-bit by 16-bit, high-speed multiplier and the 40-bit accumulators allow a very efficient implementationof even high-complexity control algorithms. Theoperations required to implement a digital loop arebasically a sequence of multiply/accumulateinstructions. The DSP core is capable of implementingsuch instructions in a very efficient way. The MACinstruction performs the following operations in onemachine cycle (33 ns in dsPIC30F devices, 24 ns indsPIC33F devices):1. Multiply two values.2. Accumulate the current multiply result toprevious sums.3. Update the registers containing the two factorswith new values for the following mac operation.4. Increment pointers so that they point to thevalues that will be used later.Efficient usage of the memory allows implementation offast accesses to locations in RAM (and in Flash) withoutreducing the overall speed of the processing unit.Specifically, one of the key problems in executing a macoperation is that while the multiply/accumulate computationalpart is performed, two new data must befetched from the RAM to be ready for the next iteration.This means that it must be possible to make a readaccessto RAM twice in one instruction cycle. Multiplesolutions are available. Microchip’s approach is to split(only for mac class instructions) RAM into two parts (X-RAM and Y-RAM) and duplicate the address and dataDS01207B-page 90© 2009 Microchip Technology Inc.

AN1207bus and the address generating hardware. Two pathsare thus available through which two new factors canbe fetched simultaneously.To complete a control loop implementation, someadditional work is needed to set up initial conditionsand usually, to check that the results are within aspecified range; however, a full control loopcomputation is normally performed in 1 to 2microseconds.THE PIDIn both the voltage and current mode control loops, inthe analog solution, the objective was to design thetransfer function of the error amplifier (GEA(s)) to makethe system stable. A similar design objective is to bereached in the digital design.A very commonly used building block is the PID (proportional,integrative, derivative). It is normally usedalso in the analog domain, and is found to be a veryeasy and useful application in the digital domain also.As it can be guessed from its name, a PID is made ofthree basic blocks whose outputs are:• Proportional to the input• The integral of the input• The derivative of the inputAlthough there are a number of ways these blocks canbe interconnected, the most traditional technique willbe investigated, where the three blocks are connectedin parallel, as shown in Figure 85.Figure 85 also shows how the PID is inserted in theblock diagram representing a system. The goal of thePID block is to generate an output u(t) that drives thesystem at hand (the “PLANT”) so that its output [y(t)]matches a reference signal [x(t)]. The input to the PIDis the error between the reference signal (ideal ordesired behavior of the PLANT) and the real outputbehavior. Obviously, the target is to operate such thatan error that is as close to zero as possible results.Comparing Figure 81 and Figure 85 it is recognizedthat GEA transforms in the PID controller, while thePLANT is the product of GM(s)GLP(s).In the following, starting from the description of a PID inthe analog domain, it will be transformed into theequivalent digital PID.For Figure 85, the equation that describes the behaviorin the continuous time domain is shown inEquation 283.EQUATION 283:de()tut () = K Pet () + K Iet ()dt + K D------------dtAnd its transfer function is (Laplace transform of theimpulse response) shown in Equation 284.EQUATION 284:K IKUs ( ) K P----- Ds 2 + K Ps + K I= + + Ks Ds = ----------------------------------------sFIGURE 85:GENERIC SYSTEM CONTROLLED BY A PIDProportionalKPUp(t)e(t)x(t)+IntegrativeKIUi(t)+U(t)PLANTy(t)DerivativeKDUd(t)© 2009 Microchip Technology Inc. DS01207B-page 91

AN1207As shown in Figure 86, there are two zeros and onepole at the origin. A high gain at low frequency is preferredto reduce DC errors, while a high gain at high frequencyshould be avoided (noise and spurious signalswould be enhanced). This is why very often the transferfunction is slightly changed to add a second pole (fp2,dashed transfer function).The next step is to transform the analog PID and itsequations in the discrete time version. To do that, amapping from the s-domain to the z-domain must beperformed using the Equation 285.EQUATION 285:1 – z – 1s → ---------------Twhere T is the sampling periodThe z-domain is the most useful domain wheresampled signals can be analyzed and systemssynthesized. This is the discrete systems counterpartof the Laplace transform. It is easy to move from thetime domain to the z-domain and vice versa through atransformation called Z-transform. One of the mostnotable features of the Z-transform is that a rationaltransfer function in s transforms in a rational transferfunction in z -1 . This means that, starting from ananalog transfer function like the one in Equation 280, atransfer function is obtained in the digital domain whichstrictly resembles it, as shown in Equation 286.EQUATION 286:Hz ( )=NA ( 1 – c rz – 1 )∏r = 1M----------------------------------------∏k = 1( 1 – d kz – 1 )There are a few possible variable transformations likethe one in Equation 285 that maps the s-domain to thez-domain. Each transformation has differentcharacteristics of how the two domains map to eachother; however, the details are beyond the scope of thisapplication note.FIGURE 86:ANALOG PID TRANSFER FUNCTIONU(s)Pole at the origin-20 db/sec+20 db/secfZ1 fZ2 fP2fDS01207B-page 92© 2009 Microchip Technology Inc.

AN1207The block diagram now is as shown in Figure 87.FIGURE 87:GENERIC SYSTEM CONTROLLED BY A DIGITAL PIDProportionalk pU p (z)VREF+E(z)+Integrativek iT---------------1 – z – 1U i (z)+U(Z)PLANTDerivativek d---- ( 1 – z – 1 )TU d (z)Using the mathematics shown in Equation 287, thetransfer function in the z-domain can easily beobtained.EQUATION 287:U P( z) = k pEz ( )U i( z)k iT= ---------------E 1 – z – 1 ( z )The results are shown in Equation 288.EQUATION 288:Uz ( )( 1 – z – 1 ) = [ K A+ K Bz – 1 + K z – 2 ]Ez ( )CGoing back to the time domain (performing the inverseZ-transform) is shown in Equation 289.k dU d( z)= ---- ( 1 – z – 1 )Ez ( ) ⇒Tk dk iTUz ( ) = k p+ --------------- ----1 – z – 1 + ( 1 – z – 1 ) Ez ( )T( k pT + k iT 2 + k d)–( k pT + 2k d)z 1 +Uz ( )= -------------------------------------------------------------------------------------------------------E dT 1 z 1( z)⇒( – )Uz ( )( 1 – z 1 ) = [ K A+ K Bz 1 + K z 2 ]Ez ( )CwhereK Ak Pk iT k d---- ; K ⎛T Bk p2 k d– + ---- ⎞k d= + + =⎝ T ⎠; K C= ----TEQUATION 289:un ( ) = un ( – 1) + K Aen ( ) + K Ben ( – 1) + K Cen ( – 2)⇒un ( ) = un ( – 1) + ( k p+ k i+ k d)en ( ) + –( k p+ 2k d) en ( – 1) + k den ( – 2)© 2009 Microchip Technology Inc. DS01207B-page 93

AN1207The meaning of such an expression is that the currentvalue of the output [u(n)] (in this case the duty cycle ofthe PWM) is computed from the value of the output atthe previous instant in time [u(n - 1)], plus the currenterror times a coefficient (KA), plus the error from previousstep times another coefficient (KB), plus the errorfrom two steps ago, times a third coefficient (KC).This is the discrete time domain equation the dsPICDSC device is requested to calculate. Note that thisoperation is performed at maximum, once per PWMperiod, T.The terms in Equation 289 can be rearranged, asshown in Equation 290.EQUATION 290:un ( ) =+ un ( – 1)++ k p[ en ( )–en ( – 1)] ++ k i[ en ( )]++ k d[ en ( )–2e( n–1) + en ( – 2)]A few comments regarding Equation 290:• The proportional contribution depends on thedifference between the current error and theprevious error.• The integrative contribution depends on thecurrent error.• The derivative contribution depends on theincrement of the error, which can be rewritten asEquation 291.1. If all errors are ‘0’, u(n) = u(n - 1).2. If there is a constant error:a) The proportional contribution is ‘0’.b) The integrative part presents a non-zerocontribution.c) The derivative part presents a zerocontribution.3. If only KP is present (KI and KD = 0) when thecurrent error is very close to the previous error,u(n) no longer changes. This explains the residualerror received in this condition. This residualerror then depends also on the resolution beingused in the ADC and the computations.4. If only KI is present, there is always a contribution,even when the e(n) is constant. Again, thetotal residual error depends on the ADC andcomputations resolution.EQUATION 291:[ en ( )–2e( n–1) + en ( – 2)] = [ en ( ) – en ( – 1)] – [ en ( – 1) – en ( – 2)] = Δe n 1,n– Δ–e n – 2,n – 1If starting from Equation 292, and nulling two out ofthree coefficients (KB =KC = 0), results inEquation 293, which means that in reality, acontribution is coming from all three building blocks.EQUATION 292:un ( ) = un ( – 1) + K Aen ( ) + K Ben ( – 1) + K Cen ( – 2)EQUATION 293:un ( ) = un ( – 1) + K Pen ( ) + K Ien ( ) + K Den ( )DS01207B-page 94© 2009 Microchip Technology Inc.

AN1207Behavior of the PIDAs can be assumed from Equation 284 andEquation 288, changing the values of KP, KI and KDchanges the behavior of the PID system, whichchanges its frequency response. It is not easy to seethe relationship between the coefficients and thetransfer function.Referring to Equation 287 in the z-domain:• If KP ≠ 0 and KI = KD = 0, the transfer function is aconstant kp• If KI ≠ 0 and KP = KD = 0, the transfer function hasa zero in the origin and a pole in z = 1• If KD ≠ 0, KP = KI = 0, the transfer function hasone zero in z = 1 and one pole in the originThe proportional term alone is capable of sensiblyreducing the error, but it cannot nullify it, because (referto Equation 290) when the error is almost constant (nomatter its absolute value), but not zero, the output fromthe PID computation is constant. This means that theproportional term can sensibly reduce the error, but atthe end a non-zero residual error always results, whichcannot be completely eliminated by the proportionalfactor only.To overcome this difficulty, the integral term representingthe memory of the system, is capable of reducingthe proportional residual error to zero. But the integralterm should be used with caution, since it can bring thesystem to oscillation. The continuous accumulation ofnon-zero values can bring the system to saturate onone side, and then to the other side, and so on.The derivative component helps the system to bereactive to sharp changes in the error value, since itscontribution is proportional to the difference betweencurrent and previous errors.Until now, nothing has been said about the values ofthe three coefficients, KP, KI and KD. There are basicallytwo methods that can be used to determine theirvalues:1. An empirical approach starting with KP ≠ 0,KI =KD = 0 and trimming the KP value until asmall residual error is received, and thenincrementing KI, until the system reaches analmost zero final error. And finally, the kd term isincremented to improve the performances of thesystem against step changes in the input error.Table 4 can be useful as a starting point tounderstand the relationship between thecoefficients and the system behavior. It shouldbe noted however, that this table is only astarting point since dissimilar systems behavedifferently.TABLE 4:ClosedLoopResponseRELATIONSHIP BETWEENCOEFFICIENTS AND SYSTEMBEHAVIORRiseTimeOvershootSettlingTimeSteadyStateErrorKP Decrease Increase Small DecreasechangeKI Decrease Increase Increase EliminateKDSmallchangeDecrease Decrease Smallchange2. The second approach is more systematic and isknown as the Ziegler/Nichols method. In thistechnique, start by incrementing the proportionalgain (while the other coefficients are zero)until the system is at the edge of stability (stepchanges are applied to the reference value).In this condition the output is an oscillation withperiod T and the corresponding coefficient is KP.The other coefficients are read from tables thatcan be found in Control Theory textbooks.It should also be noted that the full PID equation is notoften implemented. Often, only the proportional-integrationpart (PI) is implemented. This depends on thesystem and system responses needed.© 2009 Microchip Technology Inc. DS01207B-page 95

AN1207THE DIGITAL CONTROL LOOP WITH THEdsPIC DSC DEVICEHow does the PID fit into the DC-DC converter controlloops? Thinking in “digital terms” Figure 63 is redrawn,as shown in Figure 87, where the sequence of operationsis split between peripherals (hardware) of theSMPS parts and computations (firmware).The feedback voltage is converted by the on-boardADC. In the dsPIC DSC device, a 10-bit value isreturned; in reality it is known that the converter alwaysconverts two signals. This is intended to make availableto the user, at the same time, a voltage and a current.In this implementation the current measurement isnot used. Instead, a basic voltage control loop is implemented.FIGURE 88:BUCK CONVERTER VOLTAGE MODE CONTROL LOOP IMPLEMENTED ON AdsPIC ® DSC DEVICELOR1VDCC0R0VOUTR2dsPIC ® DSCDuty CycleRegisterDSP EngineMACOperation16 10+A/DPWM IPP16VREFPID CoefficientsBufferKA16X16Error SamplesBuffere(n)16KB16X16e(n - 1)KC16X16e(n - 2)32 32 32(discarded)40-bit Accumulator16Boundary Tests16PID Computation(Duty Cycle)DS01207B-page 96© 2009 Microchip Technology Inc.

AN1207The voltage from the ADC is subtracted from the referencesignal and the resulting error is fed into the DSPengine to implement the PID.The DSP engine implements Equation 289 exactly.The 40-bit accumulator in the DSP engine is used toaccumulate the previous result values, which is valueu(n) in Equation 294.EQUATION 294:un ( ) = un ( – 1) + K Aen ( ) + K Ben ( – 1) + K Cen ( – 2)The PID output (u(n)) is the current duty cycle valueand is written into the IPP PWM duty cycle register.This is almost all that is needed to implement a basicdigital loop. In reality, some attention must be paid tothe fact that, if the feedback voltage is very far from thereference voltage, large contributions to the duty cycleare accumulated. This results in the effect that the dutycycle can become too large, with a saturation effect.However, the PID can recover from this situation, but itis better to avoid it since the response time is greatlyaffected. A good practice is to clamp the duty cyclevalue to the PWM period (this is the meaning of“boundary tests” in Figure 87).In the digital implementation of the control loop, thereare some delays that must be taken into account:• Analog-to-Digital sample/convert time• PID computations time• Some non-zero delay in the power componentresponse• Low-pass filter delayAll of these delays can be summed up as this time providesa boundary condition for the sampling frequency,in that it does not make any sense to sample the systemfaster that the reverse of this time. In other words,this is the required time for any change in the system topropagate along the loop.The reverse of this delay time determines the maximumsampling frequency that is reasonable to use inthe system. Remembering the Nyquist sampling theorem,which states that to be able to reconstruct the originalsignal, the sampling frequency must be at leasttwice the maximum frequency of the signal of interest.This value of 2 is in fact only theoretical; in the realworld it must be higher. Typical values can be from 6 to10. Correspondingly, the maximum signal frequencythat can be correctly operated upon is six to ten timessmaller that the sampling frequency.To clarify the concept, look at Figure 89(A), where fs isthe sampling frequency, and fm is the maximum signalfrequency value.Optimally, trying to speed up as much as possible theoperation of the digital loop to have the smallest possibledelay in the loop, which is the maximum availablesampling frequency. But why? The key point is that ifthere is a high sampling frequency, the maximum signalfrequency is high; this means that the loop can easilyrespond to high frequency changes in theenvironmental conditions of the system. A graphicalexample is in Figure 89(B) for two different values of fs(fs1 < fs2). Keeping the same ratio between samplingfrequency and maximum allowable signal frequency,results in a larger bandwidth with fs2 compared to fs1.To further investigate the concept, suppose the inputvoltage VDC has some ripple added, and this ripple is asinusoid of frequency fO. If the sinusoid frequency issmall, the system can easily adapt the parameters ofthe converter to compensate for this sinusoidal changein the input and give a stable (without ripple) output.Now, continuously increment the sine wave frequency.Up to a certain value, the system will be able to followit and compensate; but for some value of f the systemwill fail to correctly compensate up to a situation wherethe system delay will be longer than the period of thesinusoid and the loop will completely fail to control theoutput voltage (see Figure 89(C), with somesimplifications).© 2009 Microchip Technology Inc. DS01207B-page 97

AN1207FIGURE 89:SYSTEM LOOP BANDWIDTHAND SAMPLINGFREQUENCY(A)finite set of output possible values. For example, in a10-bit ADC, only 1024 output values are available,while the input has an infinitely continuous range.So, what is the effect of such discretizations?Both of them can be considered as noise that is addedto the signals. However, the analysis of the effects ofsuch additive noise if far beyond the scope of this applicationnote. But, an important point regarding discretizationcan be introduced: how the ADC and the digitalPWM resolution will impact the behavior of the system.The minimum ADC resolution can be computed fromthe ratio of the desired output voltage amplitude andthe required precision in volts of the output voltage,according to the relationship shown in Equation 295.fmfstEQUATION 295:V OUTres = log 2----------------------------------------ΔV OUT,requested(B)A 5V nominal output when a 1% precision is required,results in Equation 296.EQUATION 296:5res = log 2--------- ≈7 bits0.05fm1fm2--------fs1fm1System Bandwidth(C)fs1fs2= -------- ⇒ fm2 > fm1fm2fs2tAs for the digital PWM peripheral, there are two differentresolutions. The digital PWM frequency resolutiondepends on the number of bits used to generate thebasic frequency. In SMPS devices the frequency of thePWM can be computed with Equation 297.EQUATION 297:A B C14, 55 • 10 6 • 64F PWM≈ ----------------------------------------PTPERwhere PTPER is the register setting the PWM frequencyfmA, B and C represent the sinusoidal superimposed signalto the nominal duty cycle, where:A = Signal is compensated by the systemB = Signal is only partially compensatedC = Signal is not compensated at allOne of the main differences between the analog andthe digital loop, is that while in the former all values intime and amplitude are continuous, in the latter timeand amplitude are both discretized. Time is discretesince, as seen above, samples of the signals havebeen taken with a fixed period repetition rate. Amplitudeis discrete since the ADC maps input values into afstThe minimum change in frequency corresponds to theminimum change in the value of the PTPER register. IndsPIC30F devices, since the three Least Significantbits (LSbs) in the register are not available, theminimum change is 8 (2 3 = 8), which corresponds to8,4 ns. Table 5 provides the frequency resolution thatcan be received for various values of the nominalfrequency. The resolution is plotted in Figure 90.DS01207B-page 98© 2009 Microchip Technology Inc.

AN1207TABLE 5:FrequencyFIGURE 90:FREQUENCY RESOLUTIONMaximumFrequencyMinimumFrequency100000 100085,98 99914,16150000 150193,55 149806,95200000 200344,23 199656,95250000 250538,10 249464,21300000 300775,19 299228,79350000 351055,58 348950,75400000 401379,31 398630,14450000 451746,44 448267,01500000 502157,03 497861,42550000 552611,14 547413,42600000 603108,81 596923,08650000 653650,11 646390,43700000 704235,09 695815,544500,00Δf4000,003500,003000,002500,00Series12000,001500,001000,00500,000,00100000 150000 200000 250000 300000 350000 400000 450000 500000 550000 600000 650000 700000Frequency© 2009 Microchip Technology Inc. DS01207B-page 99

AN1207The second resolution in PWM signals is the duty cycleresolution, which at 1.05 ns is very high.A parameter that is worth computing, is the systemoutput resolution, which is how much the output voltagewill change in response to a minimum change in thePWM duty cycle. This is a measure of the minimumcorrection of the output voltage that can be generated(see Equation 298).EQUATION 298:ΔV MINFor example, a 100 kHz PWM frequency and nominal5V output voltage results in Equation 299.EQUATION 299:V MIN=V OUT nom,• 105ns , • F PWMΔ = 5•105ns , • 100 3 = 05mV ,A final consideration is that the PWM resolution shouldbe at least one bit higher that the ADC resolution; otherwise,the output value will cross the boundarybetween two ADC values and the system will continuouslytry to reach a stable condition, oscillatingbetween these two values.CODE EXAMPLEThe block diagram in (Figure 91) shows a real implementationof a voltage mode closed loop. The codeused in this application note is available for download(see Appendix A: “Source Code”).The main program is composed of two parts:1. A set of initialization routines, where all theperipherals used (IPP PWM and IPP ADC) areprogrammed.2. A main loop. In the example (Figure 91) it isempty. This is because all the relevantoperations are performed in the ADC interruptroutine.The reason for this is that the computations (aspreviously seen) should be performed as fast aspossible to increase the bandwidth of thesystem. The main loop will be periodicallyinterrupted by the high-priority ADC InterruptService Routine (ISR), so that low priority taskscan be performed in this loop. For instance, themanagement of the user interface orcommunication to external units.The ADC interrupt, as pointed out, is the real “core” ofthe firmware. The basic operations performed are:1. Collect data from the ADC hardware.2. Compute the difference between the currentlyread voltage value of the system (VFB) and thereference voltage value.3. Implement the PID, whose output is the dutycycle.4. Clamp the computed value between a minimumand a maximum value.5. Update the duty cycle with the currentlygenerated (new) duty cycle.The processor is run from its internal Fast RC (FRC)oscillator, with a nominal frequency of 14.55 MHz. Aninternal PLL (32x) raises the operating frequency of thecore and peripherals. Taking advantage of the clockspeed and high performance DSP engine, the ADCinterrupt routine is executed in 1.4 µs, and the basicPID functionality is performed in 1.15 µs.In general terms, it is not necessary to update the dutycycle at each PWM period. As seen before, the dutycycle update frequency is what determines the maximumloop bandwidth, which is the capability of the systemto respond to fast changes in the input (lineregulation) or output (load regulation). If for instance,the PWM frequency is 200 kHz, and the voltage/currentis sampled and the duty cycle is updated every otherperiod, this results in a 100 kHz update rate, which is10 µs between two successive interactions with thesystem.If the firmware requires 1.4 µs to execute the ADC routine,8.6 µs (10 – 1.4 = 8.6) are still available to performall necessary operations, such as, communication onthe UART and/or the management of a human interface.The dsPIC DSC device is powerful enough to providethe capability to implement not only the raw controlloop, but additional functionality as well!DS01207B-page 100© 2009 Microchip Technology Inc.

AN1207FIGURE 91:PROGRAM FLOWMAINInit RoutinesInit VarsInit PortsInit I/OInit Timer1Init PWMInit ADCOutput VoltageRamp-upEndless LoopNOPADC ISRDummySelect PairInput VoltagePair AN2/AN3Output VoltageRead Output VoltageRead Input VoltageVINRETFIECompute ErrorRETFIECompute PIDBoundary ChecksRETFIE© 2009 Microchip Technology Inc. DS01207B-page 101

AN1207DETAILED CODE DESCRIPTIONIn the following section some details of the code thatimplements the basic PID functionality are analyzed.In this design, the code has been designed and testedusing Microchip’s dsPICDEM Buck DevelopmentBoard (part number DM300023).Variables DefinitionA buffer for the error values is allocated in X-RAMmemory in the near area, as shown in Example 1.EXAMPLE 1:.section PidVars_Xmem, bss, near, xmemory; Pid valuesError_n: .space 2Error_n_1: .space 2Error_n_2: .space 2Another buffer for the PID coefficients is allocated inY-RAM, again in the near area, as shown inExample 2.EXAMPLE 2:.section PidVars_Ymem, bss, near, ymemory;Pid gain valuesK_A: .space 2K_B: .space 2K_C: .space 2Some additional service variables are also allocated inthe near area, as shown in Example 3.EXAMPLE 3:MyFlag: .space 2; bit flagsVdesired: .space 2Vset: .space 2Vin: .space 2Vfb: .space 2SystemTimer: .space 2Vctrl: .space 2Code DescriptionThe main code starts with some initialization routines:• InitVarsClears the buffers and initializes the KA, KB and KCparameters. It also initializes some core registerbits to obtain the desired behavior of the DSPengine (signed mode enabled for DSP multiplyoperations, accumulator A saturation enabled,data space write saturation enabled, integer modeenabled for DSP multiply operations). Pointers areinitialized at the beginning of the two buffers.• InitPortsA few pins from port B are used as analog inputsso the configuration register must be consistentlyprogrammed. PORTE I/O pins are used by thePWM peripheral also and are initialized as outputpins.• InitIOA fixed low value is output on the PWM ports atstart-up in order to discharge any cap that could bestoring energy from previous runs.• InitTimer1Initializes Timer1 and enables interrupts.• InitPWMOne PWM channel is enabled in the followingconfiguration:a) Primary time base provides timing for thisPWM generator.b) DCx register provides duty cycleinformation for this PWM generator.c) Positive dead time actively applied for alloutput modes.d) Dead time period (0x0190).e) Trigger output for every second triggerevent.f) PWM module controls the PWMxH andPWMxL pins.g) Fault input is disabled.h) Compare value for PWM time base fortrigger the ADC module (= 8).• ADCThe converter is enabled with a clock of 13.3 MHz;pairs 0 and 1 are configured so that IRQ is generatedand the trigger is, in both cases, the PWM1generator.• StartOpsStarts the timers and all operations of the system.The target output voltage is set (VSET) and the initialoutput voltage is fixed to some small value(VDESIRED = 0x40).After the initial phase, a ramp is generated to have asmooth path from the initial zero voltage to the finalvalue. Timer1, with an interrupt rate of 1 µs, is used. Ateach timer interrupt, the desired voltage is incrementedby a fixed delta until the final desired output voltage isreached.Then the main code enters an endless loop, which duringnormal operation, is interrupted only by the ADCISRs.DS01207B-page 102© 2009 Microchip Technology Inc.

AN1207ADC Interrupt Service Routine (ISR)This is the real core of the code. The first thing to do isto determine which pair of input analog channels generatedthe interrupt. A computed GOTO is used to jumpto the corresponding piece of code. Since a voltagecontrol loop is implemented, only the output voltagevalue (label OutputValues) is of interest.Then some housekeeping is performed (pointers to thebuffer start address are initialized). Then the currentvoltage input value is read and adjusted as shown inExample 4. In this portion of code, W3 points to theADC register containing the voltage value. A left shift(multiply by two) is required since the hardware circuitto read the output voltage is a one-half resistors voltagedivider.EXAMPLE 4:; Calculate Voltage errormov [W3], W0slW0, #1, W0mov W0, VfbThe current value of the error can now be determined(see Example 5), remembering that the error is the differencebetween the desired voltage and the real voltageread through the ADC. In this portion of code, W0contains at the beginning of the real output voltagevalue and at the end the newly computed error.EXAMPLE 5:; computation of proportional error; ep = Vdesired - current output voltage; ep [W1] = Vdesired - Vfbmov Vdesired, W1sub W1, W0, W0The PID is computed using the movsac instruction first(to initialize the W6 and W7 registers and the bufferspointers), and then the mac instruction (three times), asshown in Example 6, which performs the multiply/accumulate instruction as described in Figure 81.EXAMPLE 6:movsac A, [W8]+=2, W6, [W10]+=2, W7mac W6*W7, A, [W8]+=2, W6, [W10]+=2, W7mac W6*W7, A, [W8]+=2, W6, [W10]+=2, W7mac W6*W7, A; save value roundedsac.r , -#8, [W2]At the end, the result (stored in accumulator A) is alsorounded and saved in a RAM location (VCTRL).The duty cycle value, accumulated in subsequentsteps, is stored continuously into accumulator A. Somechecks on the content of accumulator A are performedto make sure that the accumulated duty cycle neverbecomes larger that the period or, vice versa, becomestoo small.Note that, to increase the resolution for the PID coefficients,an 8.8 format is used. This means that there isan implied comma (‘ , ’) between bit 7 and bit 8 of the16-bit wide register. The nice thing of this representationis that it is also possible to use fractional numbers.In other words, a value ‘1’ in this format is representedby: 0000.0001.000.0000 = 0x0100.© 2009 Microchip Technology Inc. DS01207B-page 103

AN1207CONCLUSIONThe need for higher performance AC-to-DC and DC-to-DC converters is supported by the availability ofprocessors such as Microchip’s dsPIC DSC SMPSfamily of devices. These devices are able to performcomputational intensive algorithms, while providingspecialized peripherals.Covering all aspects of converter design is beyond thescope of this application note. The intent is to provideat the very least the basic tools needed to understandand design a working converter.A basic understanding of the main converter topologies,their requirements, and their performance is fundamentalto implementing converters where maximumperformance is achieved.The first part of this application note deals with topologies(isolated and non-isolated), and behavioral detailsof the various systems are provided. In someinstances, where appropriate, additional information ispresented, such as power consumption and efficiency.Design equations are provided for all topologies, whichserve to fill in the gap between theory and practicalimplementation. Other design approaches can be usedif desired.Digital converters are closed loop systems, whichcome with advantages as well as issues. A fast reviewof basic control theory is presented, as well as anexplanation on how to use the powerful tools that thistheory provides toward designing a stable converter.Some effort has been taken to show how these resultscan be efficiently implemented using the MicrochipdsPIC DSC SMPS family of devices. Implementation ofa PID system is shown and the code is also available(see Appendix A: “Source Code”).REFERENCES• Ned Mohan, Tore M. Undeland, William P. Robbins,“Power Electronics: Converters, Applicationsand Design”, John Wiley & Sons, Inc., 2002• Abraham I. Pressman, “Switching Power SupplyDesign”, McGraw-Hill, 1997• Lawrence R. Rabiner, Bernard Gold, “Theory andApplication of Digital Signal Processing”, Prentice-Hall,Inc., 1975• A. V. Oppenheim, R. W. Schafer, “Digital SignalProcessing”, Prentice-Hall, Inc., 1975DS01207B-page 104© 2009 Microchip Technology Inc.

AN1207APPENDIX A:SOURCE CODESoftware License AgreementThe software supplied herewith by Microchip Technology Incorporated (the “Company”) is intended and supplied to you, theCompany’s customer, for use solely and exclusively with products manufactured by the Company.The software is owned by the Company and/or its supplier, and is protected under applicable copyright laws. All rights are reserved.Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws, as well as to civilliability for the breach of the terms and conditions of this license.THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATU-TORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU-LAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FORSPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.All of the software covered in this application note isavailable as a single WinZip archive file. The archivemay be downloaded from the Microchip corporate Website at:www.microchip.com© 2009 Microchip Technology Inc. DS01207B-page 105

AN1207APPENDIX B:REVISION HISTORYRevision A (June 2008)This is the initial released version of this document.Revision B (September 2009)This revision includes the following updates, whichclarify the dsPIC DSC device families that can be usedin conjunction with this application note.• Updated the second sentence in the lastparagraph on page 98 by adding a reference tothe dsPIC30F family.• Updated the device family reference to includethe dsPIC33F part family in first paragraph of theSwitch Mode Power Supply (SMPS) dsPIC DSCDevices section.• Updated the machine cycle value device familyreferences in the eight paragraph of the SwitchMode Power Supply (SMPS) dsPIC DSC Devicessection.DS01207B-page 106© 2009 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in theintended manner and under normal conditions.• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s DataSheets. Most likely, the person doing so is engaged in theft of intellectual property.• Microchip is willing to work with the customer who is concerned about the integrity of their code.• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does notmean that we are guaranteeing the product as “unbreakable.”Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.TrademarksThe Microchip name and logo, the Microchip logo, dsPIC,KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,rfPIC and UNI/O are registered trademarks of MicrochipTechnology Incorporated in the U.S.A. and other countries.FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,MXDEV, MXLAB, SEEVAL and The Embedded ControlSolutions Company are registered trademarks of MicrochipTechnology Incorporated in the U.S.A.Analog-for-the-Digital Age, Application Maestro, CodeGuard,dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,ECONOMONITOR, FanSense, HI-TIDE, In-Circuit SerialProgramming, ICSP, Mindi, MiWi, MPASM, MPLAB Certifiedlogo, MPLIB, MPLINK, mTouch, Octopus, Omniscient CodeGeneration, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,PICtail, PIC 32 logo, REAL ICE, rfLAB, Select Mode, TotalEndurance, TSHARC, UniWinDriver, WiperLock and ZENAare trademarks of Microchip Technology Incorporated in theU.S.A. and other countries.SQTP is a service mark of Microchip Technology Incorporatedin the U.S.A.All other trademarks mentioned herein are property of theirrespective companies.© 2009, Microchip Technology Incorporated, Printed in theU.S.A., All Rights Reserved.Printed on recycled paper.Microchip received ISO/TS-16949:2002 certification for its worldwideheadquarters, design and wafer fabrication facilities in Chandler andTempe, Arizona; Gresham, Oregon and design centers in Californiaand India. The Company’s quality system processes and proceduresare for its PIC ® MCUs and dsPIC ® DSCs, KEELOQ ® code hoppingdevices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchip’s quality system for the designand manufacture of development systems is ISO 9001:2000 certified.© 2009 Microchip Technology Inc. DS01207B-page 107

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