SoC Design Flow & Tools: SoC Testing

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Direct Access SchemelAn implementation exampleUINTINTMODEOutTSELTSEL1OutputPadInputPadUINTINTMODEOutTSELTSEL2UserSignalOutputPadInputPadInputPadTMODEUINTINTMODEOutTSELTSEL3Test Control Logic36
Remarksl Advantages– Embedded cores can be tested and debugged as astand-alone device.– Transition from core-level test to chip level test issimple.– A slight increase in overall package pin count anddesign complexity.l Drawbacks– Not scalable.• The complexity of control logic and test circuitry growswith the number of embedded cores.– Long test time.• Blocks are tested sequentially.37
Page 1 and 2: SoC Design Flow & Tools:SoC Testing
Page 3 and 4: SoC Test Challenges
Page 5 and 6: The Role of Testingl The role of te
Page 7 and 8: l Fabrication defects (caused by im
Page 9 and 10: Characterization Testingl For desig
Page 11 and 12: Burn-In Testingl Occurrence of pote
Page 13 and 14: Incoming Inspectionl Type of tests-
Page 15 and 16: Test QualityNumber of acceptable pa
Page 17 and 18: Technology Trend:System-on-Board to
Page 19 and 20: Separation of Responsibilitiesl The
Page 21 and 22: Distributed Design & Testl In gener
Page 23 and 24: Test Accessl Direct access to deepl
Page 25 and 26: A Conceptual SoC TestArchitecture
Page 27 and 28: A Conceptual Test ArchitectureDACmP
Page 29 and 30: Test Access Mechanism(TAM)
Page 31 and 32: TAM Widthl Determines the test data
Page 33 and 34: TAM ImplementationslllllDirect acce
Page 35: Direct Access SchemelModification t
Page 39 and 40: Test BuslArchitecture overview.TDI/
Page 44 and 45: AMBA Bus-Based Testing44
Page 46 and 47: TransparencyDACmPSRAMSourcePCICUTSi
Page 48: Remarksl Advantages- Low area overh
Page 52 and 53: Test RaillCore level view.CoreParal
Page 54 and 55: Remarksl Advantages- FlexibleEnable
Page 56 and 57: Daisy Chain ArchitectureCore A Core
Page 58 and 59: Remarksl Different types of TAMs ma
Page 60 and 61: Core Test Wrapperl Function- Interf
Page 62 and 63: Wrapper & TAMBypassBypassBypassScan
Page 64 and 65: InTestBypassBypassBypassScan ChainS
Page 66 and 67: BypassBypassBypassBypassScan ChainS
Page 68 and 69: Core-Based Testl The core provider
Page 70 and 71: A System Chip with P1500 Wrapped Co
Page 72 and 73: The P1500 Wrapper Architecture72
Page 74 and 75: P1500 Wrapper Parametersl Bandwidth
Page 76 and 77: Problem Statementl Given the test r
Page 78 and 79: Tree Growing Approaches[Jone et al.
Page 80: ILP Formulation[Chakrabarty et al.

SoC Design Flow & Tools: SoC Testing

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