WM8962B, Rev 4.1 - Wolfson Microelectronics plc

Production DataWM8962BDIGITAL AUDIO INTERFACE - SLAVE MODEFigure 4 Audio Interface Timing – Slave ModeTest ConditionsThe following timing information is valid across the full range of recommended operating conditions.PARAMETER SYMBOL MIN TYP MAX UNITAudio Interface Timing - Slave ModeBCLK cycle time t BCY 50 nsBCLK pulse width high t BCH 20 nsBCLK pulse width low t BCL 20 nsLRCLK set-up time to BCLK rising edge t LRSU 16 nsLRCLK hold time from BCLK rising edge t LRH 10 nsDACDAT hold time from BCLK rising edge t DH 10 nsADCDAT propagation delay from BCLK falling edge t DD 14 nsDACDAT set-up time to BCLK rising edge t DS 10 nsNote:BCLK period should always be greater than or equal to MCLK period.wPD, April 2013, Rev 4.129