Digital Receiver Handbook: Basics of Software Radio

Digital Receiver Handbook: Basics of Software RadioTheory of OperationFPGA Implementation of Digital ReceiversFPGAs Tackle DSP FunctionsFigure 15Figure 16FPGAs (Field Programmable Gate Arrays) havebecome more appropriate for implementing digitalreceiver functions because of the built-in hardwaremultipliers and generous RAM. Remember that thedigital mixer section is nothing more than a hardwaremultiplier. The FIR filter also uses one multiplier foreach filter tap plus RAM for delay memory.The Pentek GateFlow ® IP Core Library for softwareradio includes fast FFT engines, radar pulse compressors,and digital receivers. These cores allow FPGAdesigners to readily incorporate these highly optimizedfunctions in FPGA-based products.Most of Pentek’s recent software radio productsinclude user-configurable FPGAs in the signal path tosupport IP cores and custom DSP algorithms. Pentekalso offers factory installation of IP cores in several ofthese products, thereby eliminating the FPGA designeffort and allowing customers to easily take advantage ofthis exciting new technology.Figure 15 above shows a dual channel A/Dconverter VIM-2 module with the Pentek GateFlowWideband Receiver Core 421 installed. This core replacesthe TI / GC1012B chip and offers higher dynamicrange and user-programmable FIR coefficients. It accepts16-bit inputs instead of the 12-bit inputs of the ASIC totake full advantage of the 14-bit A/D converters. For thelatest FPGA offerings visit the online FPGA Resource atpentek.com/gateflow.FPGAs not only offer significant advantages asspecialized replacements for standard ASIC digitalreceivers, they also provide extremely high performancesignal processing capabilities to offload these tasks fromDSP and RISC processors.An example is the Pentek GateFlow IP Core 4044k-point complex FFT. Although all GateFlow IP Coresare designed for use on any Virtex-II, Virtex-II Pro orSpartan 3 product, the Core 404 is available as a factoryinstalled option on the Model 6236 Dual ChannelReceiver VIM-2 module shown in Figure 16.In this case, real data from the A/D converter orcomplex I and Q samples from the wideband digitalreceiver can be directed into the FFT engine. The firststage performs an optional Hanning (or other) windowingfunction as a preprocessing step before the complex4k-point FFT.The output of the FFT can be optionally convertedto power by summing I 2 and Q 2 . Finally, consecutiveoutputs can be optionally averaged to reduce widebandnoise.Because of the highly-parallel architecture of this IPCore, it can sustain real time input sampling rates ofup to 160 MHz. It would take approximately eight G4PowerPCs running at 1 GHz to equal the processingpower of this impressive engine!10Pentek, Inc. • One Park Way, Upper Saddle River, NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: digrec@pentek.com • http://www.pentek.com