Digital Receiver Handbook: Basics of Software Radio

Digital Receiver Handbook: Basics of Software RadioProducts215 MHz, 12-bit A/D and FPGA-based Digital Receiver - VMEModel 6821Figure 28The Model 6821 shown in Figure 28 is a 6U singleslot board with the new AD9430 12-bit 215 MHz A/Dconverter.Capable of digitizing input signal bandwidths up to100 MHz, it is ideal for wideband applications includingradar and spread spectrum communication systems.The sampling clock can be supplied either from afront panel input or from an internal crystal oscillator.Data from the A/D converter flows into two XilinxVirtex-II Pro FPGAs where optional signal processingfunctions can be performed. The size of the FPGAs canrange from the XC2VP20 to the XC2VP50.Because the sampling rate is well beyond conventionalASIC digital downconverters, none are includedon the board.Instead, the Pentek GateFlow IP Core 422 UltraWideband Digital Downconverter can be used in one orboth of the FPGAs to perform this function. This corecan be incorporated by the customer using the GateFlowFPGA Design Kit or ordered as a factory installedoption. Visit pentek.com/gateflow for more information.Two 128 MB SDRAMs, one for each FPGA,support large memory applications such as swingingbuffers, digital filters, DSP algorithms, and digital delaylines for tracking receivers.Either two or four FPDP-II ports connect theFPGAs to external digital destinations such as processorboards, memory boards or storage devices.A VMEbus interface supports configuration of theFPGAs over the backplane and also provides data andcontrol paths for runtime applications. A VXS interfaceis optionally available.This Model is available in commercial as well asconduction-cooled versions.22Pentek, Inc. • One Park Way, Upper Saddle River, NJ 07458 • Tel: (201) 818-5900 • Fax: (201) 818-5904 • Email: digrec@pentek.com • http://www.pentek.com