AD9834

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AD9834SLEEPPRELIMINARY TECHNICAL DATAan anlog output of midscale.Low Power Control, active high digital input. SLEEP puts the AD9834 into a low power mode.Internal clocks are disabled and the DAC's current sources are turned off. The AD9834 is re-enabledby taking SLEEP low.Table I. Frequency/Phase RegistersRegister Size DescriptionFREQ0 REG 28 Bits Frequency Register 0. This definesthe output frequency,when FSELECT = 0, as a fractionof the MCLK frequency.FREQ1 REG 28 Bits Frequency Register 1. This definesthe output frequency,when FSELECT = 1, as a fractionof the MCLK frequency.PHASE0 REG 12 Bits Phase Offset Register 0. WhenPSEL = 0, the contents of thisregister are added to the outputof the phase accumulator.PHASE1 REG 12 Bits Phase Offset Register 1. WhenPSEL = 1, the contents of thisregister are added to the outputof the phase accumulator.Table 2. Frequency Register BitsD15 D14 D13D00 1 MSB 14 FREQ0 REG BITS LSB1 0 MSB 14 FREQ1 REG BITS LSBTable 3. Phase Register BitsD15 D14 D13 D12 D11D01 1 0 X MSB 12 PHASE0 REG BITS LSB1 1 1 X MSB 12 PHASE1 REG BITS LSBTable 4. Control RegisterD15 D14 D130 0 CONTROL BITSD0Table 5. Control Register BitsBit Name FunctionD13 B28 Two write operations are required toload a new word into the FREQ registers.When the complete register isbeing loaded with a new 28-bit word,B28 can be set to 1. The first write toaddress 01 or 10 contains the 14 LSBsof the frequency word. The next writeto this address will contain the 14MSBs. When B28 is set to 0, the frequencyregister operates as 2 registers,one containing the 14 MSBs and theother containing the 14 LSBs. To alterthe 14 MSBs or the 14 LSBs, asingle write is made to the FREQ addresswhile D12 of the control registerinforms the AD9834 whether the bitsare MSBs or LSBs.D12 HLB When B28 is set to 0, the 14 MSBs ofthe frequency word can be altered independentof the 14 LSBs and viceversa. A single write is made to theappropriate frequency address whilethe HLB bit indicates whether the 14bits being loaded are being transferredto the 14 MSBs or 14 LSBs of the register.This allows the user to continuouslyload the MSBs or LSBs whileignoring the remaining 14 bits. Thisis useful if the complete 28 bit resolutionis not required. When HLBequals 1, the 14 bits of data are transferredinto the 14 MSBs of the frequencyregister. When HLB equals 0,the 14 LSBs of the frequency registerare loaded.D11 FSELECT This is the FSELECT bit.D10 PSEL This is the PSEL bit.D9 PIN/SW The RESET, FSELECT, PSEL andSLEEP functions can be controlled viabits in the control register or pins.PIN/SW selects the source of controlfor these functions. When this bitequals 0, the PHASE/FREQ registersare selected using the bits FSELECTand PSEL. The device can be resetusing the RESET bit and the part ispowered down using the SLEEP12 bit.When PIN/SW equals 1, the registersare selected using the FSELECT andPSEL pins. The RESET pin is used–6–REV PrH 08/01
PRELIMINARY TECHNICAL DATAto reset the phase accumulator whilethe device is powered down using theSLEEP pin.D8 RESET This bit resets the phase accumulatorto zero which corresponds to an analogoutput of midscale. The bit is set to 1to perform a reset. The accumulatorwill remain in the reset condition untilRESET is set to 0.D7 SLEEP1 When this bit is set to 1, the internalclock is disabled. The DAC outputwill remain at its present value as theNCO is no longer accumulating.D6 SLEEP12 When this bit equals 1, the DAC ispowered down. This is useful whenthe AD9834 is used to output theNCO's MSB only. In this case, theDAC is not required so, it can bepowered down to reduce the powerconsumption.D5 OPBITEN When this bit is set to 1, the MSBfrom the phase accumulator is routedto pin SIGN BIT OUT. It can besent directly to the pin or, it can be dividedby 2 prior to being output. BitPIHB determines whether the squarewave generated by the MSB is dividedby 2 before being output. WhenOPBITEN equals 0, there is no outputat SIGN BIT OUT.AD9834D4 SIGNPIB When this bit is set to 0, the MSBfrom the phase accumulator isconnected to pin SIGN BIT OUT, thesquare wave being divided by one ordivided by two before being output.Bit PIHB determines the frequency ofthe square wave. When SIGNPIBequals 1, the on board comparator isconnected to SIGN BIT OUT. Afterfiltering the sinusoidal output from theDAC appropriately, the waveform canbe applied to the comparator togenerate a square waveform.D3 PIHB This bit is used in association withOPBITEN. When OPBITEN equals1, the MSB is output on pin SIGNBIT OUT to generate a square wave.When PIHB equals 0, the square waveis divided by 2 before being output.When PIHB equals 1, the MSB ispassed directly to the output.D2 Reserved This bit must be set to 0.D1 MODE When MODE is set to 0 with SLEEP1equal to zero, the ROM is used toconvert the phase information intoamplitude information which results ina sinusoidal signal at the output.When MODE is set to 1 and SLEEP1is set to 0, the ROM is bypassed andthe phase information from the phaseaccumulator is sent directly to theDAC which results in a ramp output.D0 Reserved This bit must be set to 0.SLEEP12SLEEP1RESETPhaseAccumulator(28 Bit)SINROM0MUX1(Low Power)10-Bit DACAD9834IOUTIOUTBMODE + SLEEP1COMPARATORVINSIGN/PIPIHB1MUX0DIV BY21MUX0DIGITALOUTPUT(enable)SIGN BIT OUTOPBITENDB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0ADDRS B28 HLB FSEL PSEL PIN/SW RESET SLEEP1 SLEEP12 OPBITEN SIGN/PI PIHB 0 MODE 0Figure 4. Function of Control BitsREV PrH 08/01–7–
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AD9834

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