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2004-01-1240 An Overview of Hardware-In-the-Loop ... - dSPACE

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technology for <strong>the</strong> EIO s<strong>of</strong>tware testing <strong>the</strong> complete I/Orange can be tested automatically.on a target. Utilization <strong>of</strong> test scripting and test stimulusgeneration technique <strong>the</strong> HIL system provided somelevel <strong>of</strong> dynamic input to <strong>the</strong> system, ra<strong>the</strong>r than just astatic set <strong>of</strong> input values.Figure 8 HIL integration <strong>of</strong> Executable I/O TestingThis implementation <strong>of</strong> HIL integrated EIO s<strong>of</strong>twaresignificantly reduced <strong>the</strong> testing time <strong>of</strong> all PCM I/Os,and provided a far more complete range <strong>of</strong> every test aswell. <strong>In</strong> later applications, using this testing very early in<strong>the</strong> development phase flagged some discrepanciesbetween <strong>the</strong> requirements, <strong>the</strong> specifications and <strong>the</strong>s<strong>of</strong>tware implementation. By discovering <strong>the</strong>sediscrepancies at this early phase, significant resourceswere saved, compared to finding <strong>the</strong>se discrepancieslater in <strong>the</strong> development cycle.UNIT LEVEL TESTING USING OLTThe next level <strong>of</strong> testing phase is Unit Level Testing(ULT) <strong>of</strong> application s<strong>of</strong>tware. ULT is a derivative <strong>of</strong>OLT. The Powertrain application s<strong>of</strong>tware consists <strong>of</strong>multiple interdependent features, and each featurecontains different level <strong>of</strong> sub-features. The featuresand sub-features <strong>of</strong> application s<strong>of</strong>tware are defined byfunctional boundaries. The features and sub-featuresare developed based on <strong>the</strong> Powertrain requirements.The features and sub-features are tested against suchdefined requirements. <strong>In</strong> ULT one piece or one unit <strong>of</strong>s<strong>of</strong>tware defined by certain functional boundaries istested. For ULT, sets <strong>of</strong> inputs are designed to exercise<strong>the</strong> specific unit <strong>of</strong> s<strong>of</strong>tware and fed into <strong>the</strong> PCM, and<strong>the</strong> output from that specific piece <strong>of</strong> s<strong>of</strong>tware ismonitored and recorded. The outputs <strong>of</strong> <strong>the</strong> s<strong>of</strong>twareare checked against <strong>the</strong> requirements for <strong>the</strong> s<strong>of</strong>twaregiven that set <strong>of</strong> inputs. Traditionally, <strong>the</strong> ULT is amanual operation using tools like a s<strong>of</strong>tware debuggerand manually stepping through s<strong>of</strong>tware code to check<strong>the</strong> values <strong>of</strong> <strong>the</strong> outputs <strong>of</strong> <strong>the</strong> s<strong>of</strong>tware, as well usingtools like an oscilloscopes and chart recorders to recordoutputs from <strong>the</strong> PCM. The HIL integration <strong>of</strong> <strong>the</strong> ULTprovided a more methodical way <strong>of</strong> completing unit testFigure 9 Open <strong>Loop</strong> PCM Application TestingINTEGRATION TESTING USING OLTOnce, sets <strong>of</strong> ULTs are completed, <strong>the</strong> next obviousstep is to recombine <strong>the</strong>se units and test on a subintegration level. The integration <strong>of</strong> features is testedusing <strong>the</strong> OLT methodology to test <strong>the</strong> interactionbetween several features. <strong>In</strong> <strong>the</strong> sub-integration level <strong>the</strong>complete s<strong>of</strong>tware is not integrated with all <strong>the</strong> requiredfeatures, but a few closely related features areintegrated as a broad feature. <strong>In</strong> this test environment<strong>the</strong> feature level inputs are provided from <strong>the</strong> HIL systemas dynamic inputs, and <strong>the</strong> outputs from <strong>the</strong> subintegrationlevel are monitored and recorded. Eventhough <strong>the</strong> input values may have some dynamicbehavior in it, <strong>the</strong> absence <strong>of</strong> dynamic plant modelprevented it from running in closed loop environment.The dynamic inputs were not based on <strong>the</strong> systemresponse output; ra<strong>the</strong>r it was a coherent set <strong>of</strong> inputdata. Refer to Figure 9 for a block diagram <strong>of</strong> open loopintegration testing. The next natural progression <strong>of</strong>testing is <strong>the</strong> verification <strong>of</strong> <strong>the</strong> complete feature inClosed <strong>Loop</strong>.PROGRESSION FROM OPEN LOOP VERIFICATIONTO CLOSED LOOP VERIFICATION<strong>In</strong> <strong>the</strong> OLT methodology <strong>of</strong> verification, <strong>the</strong> inputs to <strong>the</strong>PCM are provided during <strong>the</strong> simulation, and <strong>the</strong>actuator outputs from <strong>the</strong> PCM are monitored. Thecontrol loop feedback mechanism is not in place so <strong>the</strong>dynamic response <strong>of</strong> <strong>the</strong> PCM s<strong>of</strong>tware cannot be testedin OLT. CLT testing is necessary in order to fully validate<strong>the</strong> functionally <strong>of</strong> <strong>the</strong> PCM.

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