Spec-based verification: A new method for functional ... - Cadence

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The Specman Elite verification flow is very similar to the traditional flow, but is enhanced with theenabling technologies described above. As always, the input to the functional verification process isthe design spec (which defines the device’s architecture, functionality, and protocols) and the interfacespec (which defines the target system and the protocols between the DUT and the rest of the system).These specs are used to develop the functional test plan, which defines the verification strategy, the testenvironment, and the functionality and user scenarios that are to be tested. These tests should includetypical tests, stress tests, error tests, and corner-case tests.Once the test plan is defined, the test environment is developed. Existing code from previous projectswritten in Verilog, VHDL, or C can be used and linked into the system. The test environment includesstructs, which define the data to be generated, and spec constraints (from the interface specification,see Figure 5). Spec constraints constrain the generator to generate only legal values. The verificationenvironment also includes the data and temporal checks (see Figure 6), which define how to checkprotocols and monitor the simulations for correct behavior.Interface spec: An instruction consists of an opcode representingthe instruction set, op1, which can access registers zero throughthree, and op2, which is a byte.type command: [ADD, ADDI, SUB, SUBI, JMP, JMPR, JMPC, CALL, RETURN];type register: [REG0, REG1, REG2, REG3];struct instruction {opcode: command;op1: register;op2: byte;};Interface spec: If the opcode is jump to an address in a register (JMPR),the second operand must be zero.extend instruction {keep (opcode == JMPR) => op2 == 0;};Figure 5: Struct and spec constraint from the interface specificationInterface spec: An acknowledge must be received after 3 to 5 cyclesof when a request is seen.expect rise ('top.req') => {[3..5]; rise('top.ack')};Note: signals that are quoted represent DUT signals from the HDL.Figure 6: Temporal check from the interface specificationAt this point, a few deterministic tests can be written and run to verify that the device is getting outof reset and performing the basic operations correctly. Once this is done, instead of writing manydeterministic tests and checking them, constraint-driven tests can now be generated. Specman Elitetestbench automation can generate many tests, drive them into the device, and check that the deviceresponded according to the spec. But more importantly, the Specman Elite system collects the functionalcoverage information, showing what functionality was actually exercised. With this information, it isnow easy to know what functionality has not been covered and to write more specific test constraints(see Figure 7) that target the generator to focus on the untested functionality. This process ensures anefficient verification cycle and guarantees that each test adds new coverage.10
Functional test plan: Test the jump on carry (JMPC) opcode when thecarry bit is high.extend instruction {keep ('top.cpu.carry'== 1) => opcode == JMPC;};Note: signals that are quoted represent DUTsignals from the HDL.Figure 7: Test constraint from the functional test planCONCLUSIONThe ineffectiveness of current verification methodologies is apparent both in the proportion of timespent verifying a design versus the time spent designing it, and in the number of re-spins most designsrequire to become fully functional. The enormous resource expenditures required to verify today’scomplex designs will more than double in the next generation of complexity. Verification teams alreadyfind themselves backed into a no-win situation with only two options — miss the schedule by anindeterminate amount, or abort verification and risk an almost certain re-spin.Spec-based verification provides an effective composite of enabling technologies that automate resourceintensivemanual processes and establish qualitative metrics to ensure sufficient functional coverage.Using these technologies increases the quality of the design while reducing the resources needed toimplement a powerful verification methodology. Verification engineers report experiencing a two- tofour-fold reduction in the verification schedule, while achieving significantly higher verification quality.11
Page 1 and 2: WHITE PAPERSPEC-BASED VERIFICATIONA
Page 3 and 4: ABSTRACTDue to the increasing compl
Page 5 and 6: The relative inefficiency with whic
Page 7 and 8: COVERAGE METRICSMeasuring progress
Page 9 and 10: The coverage information can also b
Page 11: Although temporal checks can be don

Spec-based verification: A new method for functional ... - Cadence

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