Spec-based verification: A new method for functional ... - Cadence

ABSTRACTDue to the increasing complexity of today’s systems and ASICs, functional verification has become a majorbottleneck in the design process. Design teams reportedly spend as much as 50 to 70 percent of their timeand resources on functional verification. This paper presents a new methodology for functionally verifyingsystems and ASICs: spec-based verification — an automated and measurable approach to verification thatenables more effective verification methodologies while cutting the overall resource investment in half.INTRODUCTIONIn the past decade, the electronics industry has successfully focused on automating the process of physicaldesign (place-and-route) and design implementation (logic synthesis). However, the process of verifyingdesign functionality has been relatively neglected. Advances in verification have centered primarily onincreasing the speed of simulation, not on automating the verification methodology as a whole.With design complexities increasing exponentially, functional verification has become the main bottleneckof the design process. Faster simulators are only part of the solution. Enabling the execution of morecycles provides some benefit, but often many of these cycles are wasted because they add no additionaldesign coverage.The first step toward improving the efficiency of functional verification for large, complex designs isto raise the level of abstraction of the verification environment to the specification level. The commonspecifications driving the verification process are the design spec, the interface spec, and the functionaltest plan. The verification team can develop and implement a comprehensive verification strategy onlywhen the rules defined in these specifications can be captured in an executable form. However, raisingthe level of abstraction is insufficient, in and of itself. Once these rules have been captured, the task ofgenerating tests and checking results must be automated for the team to have any hope of attaining fullfunctional coverage within reasonable time and resource budgets.Spec-based verification addresses the functional verification bottleneck in a manner similar to the waythe introduction of logic synthesis tools addressed the design challenges posed by increasing designcomplexity. First came the hardware description languages (HDLs) such as Verilog ® and VHDL, which raisedthe level of abstraction from gate-level designs to register-transfer-level (RTL) designs, thereby makinglarge designs much more manageable. However, not until the introduction of logic synthesis automatingthe translation of RTL designs to gates did the real breakthrough occur in time and resource reduction.Similarly, the real value of spec-based verification is created by a composite of features that deliverautomation: a spec-based verification environment, automatic generation of high-quality tests, data andtemporal checkers, and accurate measurement and analysis of functional coverage. With an automatedfunctional verification approach at the center of the verification methodology, the designer gains thethree essential elements needed to overcome the verification bottleneck: quality, productivity, andpredictability. Verification methodologies that incorporate spec-based verification produce reusableverification environments, shorten the verification cycle, and reduce the risk of costly silicon re-spins.THE VERIFICATION CHALLENGEThe dynamics at the root of most verification bottlenecks are the relationships between designcomplexity, verification complexity, engineering resources, and time constraints. As designs grow morecomplex, the verification problems they pose grow exponentially — that is to say, as designs double insize, the verification effort can easily quadruple. As a result, the verification effort can consume as muchas 50 to 70 percent of the entire engineering budget.Unfortunately, neither the schedule nor the available engineering resources offer much in the way offlexibility. More importantly, the cost of missing a time-to-market schedule can force design teams toterminate the verification effort prematurely. This leads to incomplete and inadequate functionalcoverage, creating the potential for a pattern of debug cycles, re-designs, and re-spins that erode theprofitability and deliverability of the end product. Thus, ASIC design quality becomes a function of theverification schedule, rather than the verification metrics.1