Spec-based verification: A new method for functional ... - Cadence

The coverage information can also be crossed, providing information on interrelated functionality.This "querying" ability answers questions about the simultaneous occurrence of certain functions.For example, in a processor design, the verification engineer can cross information about instructions,addressing modes and machine state to see exactly how many times each instruction was executed usingthe different addressing modes for every machine state.Using functional coverage analysis, the engineer finally has a clear indication of which functionality hasbeen exercised and, more importantly, which functionality has not. This focuses the verification effortand eliminates superfluous or redundant tests, ensuring that every test adds coverage. In so doing, theavailability of functional coverage analysis has opened the door to major advancements in verificationmethodologies.The ability to generate clear reports showing which parts of the functional test plan were tested hasenabled a new approach to verification. Beginning with a base of automated tests, coverage reportsare generated to indicate which parts of the functional test plan were exercised. This allows the engineerto close quickly on significant functional coverage of the device with minimal effort. Afterward, the onlyadditional effort required is to generate tests focused on the functionality not yet covered. The coveragereports after each set of tests direct the verification engineer to the types of tests to focus on next.Deterministic tests are needed only for the corner cases that were not reached over the course ofautomated testing. This minimizes the time spent writing deterministic tests.Functional coverage reports are also an essential tool for verification managers. They help monitor theprogress of the verification effort, provide a clear view of the state of the verification, and accuratelydetermine the moment the device is ready to be fabricated.Functional coverage reports also enable the verification engineer to verify the effectiveness of the tests.Once a certain functionality has been tested enough (according to the metrics set by the engineer), otherfunctionality can be targeted and tests that add no new coverage can be discarded. There is no need tocontinue testing "just in case."The impact on the verification schedule when using this coverage approach is significant. It eliminatesmuch of the manual-intensive work of developing the deterministic tests, saving many of frustratingwork. It also significantly reduces the risk of sending the device to production while part of itsfunctionality has not been properly tested. This coverage approach eliminates silicon re-spins, whichin turn saves millions of dollars.CONSTRAINT-DRIVEN GENERATIONThe one feature spec-based verification offers that most significantly contributes to reducing theverification schedule is automated test generation. Armed with a constraint-driven test generator, aspec-based verification methodology can slash weeks or even months off the verification schedule,while placing enormous power in the hands of the engineer.Current cycle’s HDLsignal and register valuesTest constraintsSteer generation totarget areas• Target areas• Weights/probabilities• Corner-case tests• Structured sequences• Bug bypassesConstraint solverNext cycle’s stimulusSpec constraintsDefine what is legal• Protocols• I/O relationships• Context dependencies• Input definitionHDL simulationFigure 3: The constraint solver is the core technology enabling constraint-driven generation7