A Rail-to-Rail Amplifier Input Stage - Analog and Mixed Signal ...

272 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 2, FEBRUARY 2005Fig. 4.Programmable level shifting (PLS) circuitry.introduced by gate leakage via tunneling effects are sufficientlylarge, and are thus neglected in this analysis.Fig. 3. Obtaining constant transconductance by shifting the common-moderange of the input pairs to overlap transition regions.To overcome these problems, a technique that uses parallelsame channel differential pairs was introduced [15]. This techniqueis similar to [3] in that it shifts the common-mode rangeof one of the differential pairs. The primary difference is thatrather than overlapping transition regions to obtain constanttransconductance, the authors use feedforward cancellation tomaintain constant when both of the input pairs are operating.Since only one type of differential pair is used, the matchingof the the two input transconductors is much less sensitive toprocess variations. Still, the overall fluctuation in transconductanceof this circuit was nearly . Also, including thefeedforward transconductor, three differential pairs are used, aswell as some additional biasing circuitry, which increases thepower consumption of the amplifier.For simplicity and accuracy, it is best to use a single differentialpair at the input. In this case, the common-mode range of theinput pair must somehow be extended to accept rail-to-rail signals.In the past, this has been done using multiple input floatinggate transistors (MIFGs). The signal is attenuated using capacitivevoltage division before it is processed by the amplifier [1],[4]. The ratio of the MIFG capacitors is set so the input signalis attenuated enough to always reside within the common-moderange of the actual differential pair. To ensure the signal is sufficientlyattenuated, the capacitor ratio in these architectures isusually set to around five, resulting in an attenuation of six [4].This adversely affects the gain-bandwidth product (GBW) aswell as the noise response of the amplifier. Furthermore, eventhese architectures that use a single input differential pair exhibitsome variance in the due to lambda effect on the tailcurrent. As the common mode rises or falls, so does of thetransistor supplying the tail current, and accordingly, the current’smagnitude. Circuit simulations result in almost 3% deviationin across rail-to-rail common-mode inputs of a circuitimplemented in this way.In this paper, a new input stage for rail-to-rail operationis introduced, which makes use of a single input differentialpair. MIFG transistors are used, but feedback circuitryallows for a much lower attenuation than those previouslyreported. Rail-to-rail operation is achieved by shifting the inputcommon-mode level to a fixed dc level before the signal is inputto the differential pair. It is assumed that any time constantsII. PROGRAMMABLE LEVEL SHIFTERSNear zero variance in can be achieved by shifting thecommon-mode component of the input signal to a fixed levelthat resides within the common-mode range of the input differentialpair. Since the amount of shift required is dependent on thecommon-mode level of the input, programmable level shifting(PLS) circuitry is needed. A simple, highly programmable levelshifter can be created with a MIFG transistor in a source followerconfiguration, as displayed in Fig. 4. One terminal tothe MIFG transistor, , serves as the input to the circuit. Theother terminal, , determines the amount of shift by programmingthe effective threshold voltage of as seen from . Theamount of shift obtained from a transistor in the source followerconfiguration is governed by the gate-to-source voltageFor, the resulting gate voltagein Fig. 4 of the MIFG transistor with two inputs isCombining (1) and (2), the amount of shift from the point ofview of the input terminal is a recursive function of , determinedto beDefining as the effective threshold voltage as seen from ,the amount of shift from to is nowwhere(1)(2)(3)(4)(5)(6)Since can be either a positive or negative value, canalso be programmed in either direction, with the amount of shiftobtainable depending on the ratio of to .Nextwe

FISCHER et al.: RAIL-TO-RAIL AMPLIFIER INPUT STAGE 273Fig. 5.Rail-to-rail input stage.explore how to find a suitable value of to shift the commonmodelevel of differential signals to a constant value.III. FEEDBACK CIRCUITRYTwo programmable level shifters from the above sectionare now used as a pre-stage to a typical differential pair. Thecommon-mode level of the input signals is shifted to a constantvalue, yielding consistent operation independent of thecommon mode. In order to correctly program the level shifters,the common-mode information must be extracted from thecircuit, and fed back to the programming input, of Fig. 4.This is done using the architecture displayed in Fig. 5. Thesource voltage of the differential pair, labeled in Fig. 5 as ,behaves as an ac ground for differential inputs, and nearlyas a buffer for common-mode inputs. If this voltage remainsconstant, so will the magnitude of the tail current, resultingin near zero variation in of the differential pair. Any dcvalue that keeps the differential pair operating in the desiredsaturation region can be used as a reference. For convenience,the gate/drain voltage of , , is used for comparing .This difference is magnified and returned to the PLSs as .The resulting feedback voltage becomes:(7)stability analysis of the feedback loop is performed to ensureproper operation of the circuit.A. GBW and BiasingSince this design first attenuates the input signal before it isprocessed by the amplifier, the gain bandwidth product will bereduced. It is thus desirable to make this reduction as small aspossible. To achieve consistent rail-to-rail operation, the minimumattenuation can be obtained by setting in Fig. 5.There are two necessary conditions for using this attenuation.First, the feedback amplifier, , should have rail-to-rail outputsignal swing. Second, the conditionshould be met,where is the common-mode level of the input. This impliesthat the circuit should be designed such that when , is zero,should equal .The first requirement, that the feedback amplifier, has arail-to-rail output swing, is easily met by using an operationaltransconductance amplifier (OTA) based on three current mirrors[17]. The second requirement, thatcan be accomplishedthrough careful design of the circuit in Fig. 5, usingthe following relationships:(8)(9)Due to the negative feedback, if the gain of the amplifier is largeenough, is forced to be approximately equal to , and aconstant current is supplied to the differential pair regardless ofthe common mode. Also, since is equal to , the magnitudeof the tail current becomes precisely (neglecting devicemismatch) equal to the reference current.IV. DESIGN CONSIDERATIONSSeveral considerations need to be made in the design of thisamplifier. Two primary concerns in MIFG design are area andbandwidth. The addition of capacitors will increase the areaof the circuit compared to traditional amplifier design. Also,the attenuative effect of these capacitors reduces the effectivetransconductance of the input stage, degrading the GBW of theamplifier. One goal of this design should thus be to make theseeffects as small as possible. Proper biasing can help improve thecircuit performance, and minimize the required area. Finally, aSolving (2) and (8) yieldsCombining (7)–(12)(10)(11)(12)(13)

274 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 2, FEBRUARY 2005Fig. 6. Reference generation for the rail-to-rail input stage to ensure that V 0V.where . Solving for , for sufficientlylarge(14)Since , , and are design variables for thedifferential pair, is solved for in terms of the other parameters.Settingand solving (14) foryields (15) shown at the bottom of the page. As can be seenfrom (15), using an aspect ratio design method for obtainingis susceptible to process variations in , ,, and . Also, depending on the design of the rest ofthe amplifier, may need to be large to satisfy (15).This implies that the size of the capacitors and will needto be larger as well, producing concerns about the area of theamplifier. To overcome these problems, we can achieve the desiredresult by generating a new reference for comparing .This can be accomplished using the circuit in Fig. 6. For this circuit,, ,, and . An important considerationin the design of this reference generator is to keep transistorin the saturation region. At the cost of added power consumption,this technique is more robust in the presence of fabricationtolerances because the desired reference is created basedon transistor matching rather than single transistor characteristics.Furthermore, we gain a degree of freedom in the designof the PLS transistors. Smaller transistors can be used, yieldingsmaller floating gate capacitors, and less area.To illustrate the more robust nature of the circuit in Fig. 6 ascompared to that of Fig. 5 in regards to fluctuation, MonteCarlo simulations were run on each circuit. MOSFET thresholdvoltage and mobility were each varied using a normal distributionwhere 5% variation corresponds to . The POLY-POLY2sheet capacitance was also varied with a normal distributionwith 10% . The circuits were simulated 100 times each, andthe variations of fluctuation over rail-to-rail common-modeinput are plotted as Figs. 7 and 8. As expected, the fluctuationfor the circuit in Fig. 5 is more sensitive to process variationscompared to the circuit in Fig. 6. The standard deviationswere simulated as 0.645% and 0.017% for Figs. 5 and 6,respectively.B. AreaTo minimize the area of the amplifier, the capacitors should bedesigned as small as possible. A traditional MIFG design ruleis to make the floating gate capacitor 5–10 times the sum ofthe parasitic capacitance connected to the floating node. UsingMIFG transistors thus usually comes with the cost of drasticallyincreasing the necessary silicon area. In the case of this amplifier,the negative feedback partially compensates for the effectsof the parasitics. The effects of the capacitance associated withfrom Fig. 5 on transconductance magnitude and transconductancefluctuation are now analyzed in order to minimize thearea associated with this input stage.Considering the small-signal equivalent to the circuit inFigs. 5 and 6, the differential output current of the transconductorwill be(16)Transistors and are matched, thus ,and(17)Considering the source follower configurations of and ,and assuming(18)(19)(15)

FISCHER et al.: RAIL-TO-RAIL AMPLIFIER INPUT STAGE 275Using the common-mode representation of differential signals(24)(25)whereandis the common-mode component to the input signal,is the differential input. Solving (17)–(25), we obtain:(26)Thus, yielding a total effective transconductance ofFig. 7. Simulated statistical distribution of g fluctuation in the presence ofprocess variation for the circuit in Fig. 5.(27)Some attenuation in transconductance, and in turn the GBW,can not be avoided due to the nature of floating gate transistors.In order to minimize the effects of , , and on thisattenuation, it should be ensured that(28)However, this is perhaps not the best option. If and arereduced in size, the die area will become smaller at the cost ofreducing the effective transconductance of the input stage.This degradation can be compensated for by widening thedifferential pair driver transistors, and . Given a certainfloating gate capacitor size, the aspect ratios of the driver transistorscan be calculated by substitutinginto (27) and solving for . Doing so yieldsFig. 8. Simulated statistical distribution of g fluctuation in the presence ofprocess variation for the circuit in Fig. 6.Assuming the parasitic capacitance ,, andwhere(20)(21)(22)The voltage, , behaves as an ac ground for the differentialvoltages of and , and as a source follower for commonmodesignals. Assuming(23)(29)The effects of capacitor sizes on transconductance fluctuationis now analyzed. Note that the transconductance of the inputstage will deviate from its nominal value as a result of changesin the voltage due to effects on transistor . Using(18)–(25), and solving for yields (30) shown at the bottomof the page. For sufficiently large , can be approximatedwith(31)As long as the product is large, variations in willbe small, resulting in near zero fluctuations in the input stagetransconductance across all common-mode input levels withinthe supply range.To save silicon area, we recommend settingand compensating for the additional attenuation by sizingthe driver transistors and according to (29). Designingthe floating gate transistors in this way offers large savings incapacitor area when compared to traditional designs that set the(30)

276 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 2, FEBRUARY 2005Fig. 9. Simulated and derived ac magnitude response of V =V .Fig. 10. Simulated and derived ac phase response of V =V .floating capacitors equal to 5–10 times the size of the parasitics[1], [4].C. Feedback Loop StabilityAs with any negative feedback system, it is important to considerthe circuit stability. In the entire loop, there are four polesand two zeroes. If the feedback amplifier in Fig. 5, is implementedwith an OTA having transconductance , it will contributetwo poles to the system. The dominant pole of the systemwill be associated with the output of the OTA, and a nondominantpole will be associated with its internal node. A third poleand one zero is due to the MIFG level shifters, and the final poleand zero is due to the differential pair, which for common-modevoltages behaves as a source follower. For this analysis, onlythe three most dominant poles and none of the zeros are considered.The capacitive load of the source followers consistsof parasitic source to bulk and gate-to-source capacitors. Theseare assumed to be sufficiently small such that the zero and thepossibility of complex conjugate poles in the source followersis neglected. The first nondominant pole, is from theOTA, and the second, , is the smaller of the remaining two.Since for differential inputs, the voltage in Fig. 5 behavesas an ac ground, only changes in the common-mode level ofthe input, , are considered. Assuming low-frequency unitygain for the source followers and solving the feedback circuit foryields the third-order transfer function shown in (32)at the bottom of the page, where is the total parasitic capacitanceassociated with the gate of transistor from Fig. 5.Using the Routh stability criteria, the circuit will be stable whenthe following condition is met:(33)Fig. 11. Simulated and derived step response of V =V .For simplicity, assume thatso that for stabilityit is sufficient to ensure that. Thiscondition is easily met considering the fact that is due to asource follower circuit, and will typically be located at very highfrequencies. Assuming that of the feedback OTA is comparablein magnitude to the source follower transistor’s transconductance,for stability, it should be ensured that in Fig. 5is greater than the parasitic capacitances located at the nodesand . Note that since behaves nearly as a buffer forcommon-mode changes of and , the effects of the parasiticgate-to-source capacitors and , can be neglected.To verify (32), the ac magnitude, ac phase and step responseswere obtained via transistor level simulations, and compared to(32)

FISCHER et al.: RAIL-TO-RAIL AMPLIFIER INPUT STAGE 277Fig. 12.Amplifier Schematic.its equivalent mathematical response. These are plotted, respectively,in Figs. 9–11. As seen by these figures, (32) is a sufficientapproximation to the simulated behavior of the feedback.The parameters extracted from the simulation and used in evaluating(32) are 8pF, 4pF, 0.35 pF,30 Mrad/s, 100 Mrad/s, 378 A/V.D. Noise and LinearityThe noise introduced by the feedback in this circuit willappear as a voltage at the node in Fig. 5, which is a commonvoltage to both input transistors. Thus, the feedback noise willbe cancelled by the subtraction operation of the differentialpair. However, while the feedback itself does not introduceadditional noise, the input referred noise of this topology willslightly suffer due to the first stage attenuating effect of MIFGtransistors. If this attenuation is not excessive, the overall noiseshould be comparable to other rail-to-rail amplifier architecturesthat employ multiple differential pairs. For instance,assume, resulting in an attenuation of two. Theinput referred noise will thus be increased by a factor of twoas compared to a traditional single channel differential pair.Now consider a rail-to-rail topology that uses complimentarydifferential pairs [3]. The transconductance of the n-channeland p-channel differential pairs are designed to be equal, andthus their noise contributions will also be the same. The inputreferred noise of these architectures are also twice as large as atraditional single channel differential pair.This topology inherently possesses two linearization techniquesfor the differential – characteristics of the differentialpairs. The first linearity enhancement results from the attenuationof the input. Assume the – characteristics of a traditionaldifferential pair can be sufficiently expressed as a third-orderTaylor series where(34)where is the differential output current and is the differentialinput of the transconductor, resulting inFig. 13. Micrograph of the amplifier.and[18]. Including the input attenuationof the proposed amplifier, the – characteristics will be(35)resulting in(36)(37)

278 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 2, FEBRUARY 2005Fig. 15.Input stage transconductance versus input common mode.The second linearization technique inherent to this topologylies in the fact that the feedback fixes the operating point of thedifferential pair. Much of the third-order nonlinearity in traditionaldifferential pairs is a result of -effects on the tail currentsource transistor modulating the second-order effects ofthe differential pair [19]. These second-order effects appear asa common-mode signal at the coupled source of the driver transistors.The feedback used in this paper successfully tracks andcompensates for this error via the feedback voltage, .V. EXPERIMENTAL RESULTSThe output current of the input stage went to a folded cascodecircuit for gain enhancement, followed by the rail-to-railclass-AB output stage from [3]. The complete amplifierschematic is shown in Fig. 12. The suggested biasing improvementsdiscussed in Section IV-A and displayed in Fig. 6were developed after fabrication and verification, thus theexperimental results provided here are only for the input stagedisplayed in Fig. 5. The circuit was fabricated through, andthanks to, MOSIS using AMIs 0.5- m process. A micrographis displayed in Fig. 13. Symmetric supply voltages of 1.5 Vwere used. Since the focus of this paper is on a rail-to-railinput stage, the measurement results have been divided intotwo subsections. Because the class-AB output stage limits theamplitudes of signals to the supply levels, the input transconductorwas first characterized. The second section contains dataon the entire amplifier, which includes the class-AB outputstage. Five chips were received from MOSIS, and no significantdifferences were observed between them.Fig. 14.Experimental results. (a) Common-mode input. (b) Differential input.(c) Output voltage, where V = 1000I in response to an input equal to thecommon-mode signal of (a) added to the differential signal of (b).If this technique offers a 6 dB improvement inand 12 dB improvement in in the differential – conversionas compared to a traditional differential pair.A. Input TransconductorThe output current of the input transconductor was taken fromthe output of the folded cascode stage, of Fig. 12. To measurethe common-mode range of the input, a common-mode50-Hz triangular signal with 4.4- amplitude [shown inFig. 14(a)] was added to a differentially applied sinusoid

FISCHER et al.: RAIL-TO-RAIL AMPLIFIER INPUT STAGE 279Fig. 16.AC gain of the amplifier versus frequency.Fig. 17.Rail-to-rail unity gain step response.[shown in Fig. 14(b)]. The output current of the transconductorwas loaded with a 1-k resistor, creating the outputvoltage shown in Fig. 14(c). The output of the transconductanceamplifier remained virtually unchanged, regardless of thecommon-mode level, which ranged from 2.2 to 2.2.A plot of the input stage transconductance against the inputcommon-mode level is given in Fig. 15. The transconductancevaried by only 0.35 for rail-to-rail common-mode levelsof 1.5 V to 1.5 V. The previous best reported results were1.5 . Beyond the rails, from 2 to 2 V, the change intransconductance was just 1 .B. Entire Amplifier With Rail-to-Rail Input Stage and Class-ABOutput StageThe following experimental results are for the complete operationalamplifier. The ac open loop gain characteristics of theamplifier are displayed in Fig. 16. The GBW of the amplifierwas 1.17 MHz, with a phase margin of 54 Since one of the

280 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 2, FEBRUARY 2005Fig. 18. A 2.3-V , 100-kHz unity gain step response.TABLE ITHIS WORK TO PREVIOUS WORKprimary applications of a rail-to-rail amplifier is a buffer, theamplifier was placed in the unity-gain feedback configuration.Fig. 17 shows the response to a rail-to-rail step input. Fig. 18shows the response to a 2.3-V step input. The overshoot was10% and the 2% settling time was 1 . Since linearity is a concernin buffer design, the total harmonic distortion was measured,and plotted against different amplitudes and frequenciesin Fig. 19. The spectrum of one such measurement is given inFig. 20. This spectrum corresponds to the time-domain outputsignal provided in Fig. 21. Table I provides a comparison ofthis work to previous work on this topic. Please note that thearea could have been reduced to 21 mm at the cost of 300 Wof power using the techniques described in Sections IV-A andB. Circuit simulations display comparable performance parametersto those experimentally verified in this paper.VI. CONCLUSIONFig. 19.THD versus input amplitude and frequency.A new method for achieving constant in a rail-to-rail amplifierwas introduced. It uses only one input differential pair bymaking use of programmable level shifters via MIFG transistorsin the source follower configuration. The common mode is

FISCHER et al.: RAIL-TO-RAIL AMPLIFIER INPUT STAGE 281Fig. 20. Output spectrum of the amplifier in the voltage follower configuration for V =1:4sin21000t. SFDR = 70 dB.Fig. 21. Time-domain waveform corresponding to the spectrum in Fig. 20.shifted to a constant value before the signal is input to the differentialpair. Since the common-mode level of the differentialpair is fixed, consistent operation for rail-to-rail common-modeinputs is achieved. Furthermore, since only one differential pairwas used, there is no degradation in the CMRR for any inputcommon-mode levels, which is a problem for rail-to-rail architecturesthat use complimentary input differential pairs. Experimentalmeasurements of this amplifier showed only 0.35deviation in the input stage transconductance, whereas the bestpreviously reported was .REFERENCES[1] F. You, S. H. K. Embabi, and E. Sánchez-Sinencio, “Low-voltage classAB buffers with quiescent current control,” IEEE J. Solid-State Circuits,vol. 33, no. 6, pp. 915–920, Jun. 1998.[2] T. W. Fischer and A. I. Karsilayan, “Rail-to-rail amplifier input stagewith constant g and common-mode elimination,” Electron. Lett., vol.38, no. 24, pp. 1491–1492, Nov. 2002.[3] M. Wang, T. L. Mayhugh, S. H. K. Embabi, and E. Sánchez-Sinencio,“Constant- g rail-to-rail CMOS Op-amp input stage with overlappedtransition regions,” IEEE J. Solid-State Circuits, vol. 34, no. 2, pp.148–156, Feb. 1999.

282 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 2, FEBRUARY 2005[4] J. Ramirez-Angulo, R. G. Carvajal, J. Tombs, and A. Torralba, “LowvoltageCMOS op-amp with rail-to-rail input and output signal swingfor continuous-time signal processing using multiple-input floating-gatetransistors,” IEEE Trans. Circuits Syst. II, Anal. Digit. Signal Process.,vol. 48, no. 1, pp. 111–116, Jan. 2001.[5] W. Redman-White, “A high bandwidth constant g and slew-raterail-to-rail CMOS input circuit and its application to analog cell for lowvoltage VLSI systems,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp.701–712, May 1997.[6] R. Hogervorst, R. J. Wiegerink, P. A. L. de Jong, J. Fonderie, R. F.Wassenaar, and J. H. Huijsing, “CMOS low-voltage operational amplifierswith constant-g rail-to-rail input stage,” in Proc. IEEE Int. Symp.Circuits Syst. (ISCAS’92), 1992, pp. 2876–2879.[7] R. Hogervorst, J. P. Tero, and J. H. Huijsing, “Compact CMOS constantgrail-to-rail input stage with g -control by an electronic zener diode,”IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 1034–1040, Jul. 1996.[8] K. Nagaraj, “Constant transconductance CMOS amplifier input stagewith rail-to-rail input common-mode voltage range,” IEEE Trans. CircuitsSyst. II, Analog Digit. Signal Process., vol. 42, no. 5, pp. 366–368,May 1995.[9] G. Ferri and W. Sansen, “A rail-to-rail constant- g low-voltage CMOSoperational transconductance amplifier,” IEEE J. Solid-State Circuits,vol. 32, no. 10, pp. 1563–1567, Oct. 1997.[10] J. F. Duque-Carrillo, J. M. Carrillo, J. L. Ausin, and E. Sánchez-Sinencio, “Robust and universal constant-g circuit technique,” Electron.Lett., vol. 38, no. 9, pp. 396–397, Apr. 2002.[11] J. M. Carrillo, J. F. Duque-Carrillo, G. Torelli, and J. L. Ausin, “Generalpurpose rail-to-rail input circuit with constant behavior for VLSI celllibraries,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS’02), vol. 3,May 2002, pp. 607–610.[12] J. M. Carrillo, J. F. Duque-Carrillo, J. L. Ausin, J. M. Valverde, and G.Torelli, “Common-mode response shaping in rail-to-rail op-amp inputstages,” Electron. Lett., vol. 38, no. 25, pp. 1615–1616, 2002.[13] S. Sakurai and M. Ismail, “Robust design of rail-to-rail CMOS operationalamplifiers for a low power supply voltage,” IEEE J. Solid-StateCircuits, vol. 31, no. 2, pp. 146–156, Feb. 1996.[14] C. Hwang, A. Motamed, and M. Ismail, “Universal constant-ginput-stage architectures for low-voltage Op Amps,” IEEE Trans.Circuits Syst. I, Fundam. Theory Appl., vol. 42, no. 11, pp. 886–895,Nov. 1995.[15] J. M. Carrillo, J. F. Duque-Carrillo, G. Torelli, and J. L. Ausin, “Constant-g constant-slew-rate high-bandwidth low-voltage rail-to-railCMOS input stage for VLSI cell libraries,” IEEE J. Solid-State Circuits,vol. 38, no. 8, pp. 1364–1372, Aug. 2003.[16] F. You, S. H. K. Embabi, and E. Sánchez-Sinencio, “On the commonmoderejection ratio in low voltage operational amplifiers with complementaryn-P input pairs,” IEEE Trans. Circuits Syst. II, Analog Digit.Signal Process., vol. 44, no. 8, pp. 678–683, Aug. 1997.[17] E. Sánchez-Sinencio and J. Silva-Martinez, “CMOS transconductanceamplifiers, architectures and active filters: A tutorial,” Proc. IEE., Circuits,Devices Syst., vol. 147, no. 1, pp. 3–12, 2000.[18] E. A. Klumperink and B. Nauta, “Systematic comparison of HF CMOStransconductors,” IEEE Trans. Circuits Syst. II, Analog Digit. SignalProcess., vol. 50, no. 10, pp. 728–741, Oct. 2003.[19] A. Nedungadi and T. R. Viswanathan, “Design of linear CMOStransconductance elements,” IEEE Trans. Circuits Syst., vol. CAS-31,no. 10, pp. 891–894, Oct. 1984.Timothy Wayne Fischer received the Bachelor’sdegree in computer engineering from Texas A&MUniversity, College Station, in 2001. He is currentlyworking toward the Ph.D. degree in the area ofanalog and mixed-signal electronics in the ElectricalEngineering Department of the same University.Since 2002, he has been employed as a Lecturerand Research Assistant at Texas A&M University.His research interests include adaptive circuits, continuous-timefilters, low-voltage low-power CMOScircuits, and CMOS computer-aided design.Aydın İlker Karşilayan received the B.S. andM.S. degrees in electrical engineering from BilkentUniversity, Ankara, Turkey, and the Ph.D. degreefrom Portland State University, Portland, OR, in1993, 1995, and 2000, respectively.In 2000, he joined the faculty of Texas A&MUniversity, College Station, where he is currently anAssistant Professor of Electrical Engineering. Hisresearch interests are in the area of high-frequencyanalog filters, automatic tuning, mixed-mode integratedciruit design, and RF communication circuits.Dr. Karşilayan served as an Associate Editor of the IEEE TRANSACTIONS ONCIRCUITS AND SYSTEMS— I: REGULAR PAPERS from 2002 to 2004, in the areaof Analog Circuits and Filters.Edgar Sánchez-Sinencio (F’92) received the professionaldegree in communications and electronic engineeringfrom the National Polytechnic Institute ofMexico, Mexico City, Mexico, the M.S.E.E. degreefrom Stanford University, CA, and the Ph.D. degreefrom the University of Illinois at Champaign-Urbana,in 1966, 1970, and 1973, respectively.He is currently the TI J. Kilby Chair Professorand Director of the Analog and Mixed Signal Centerat Texas A&M University, College Station. Hispresent interests are in the area of active filter design,RF-communication circuits and analog and mixed-mode circuit design.Prof. Sánchez-Sinencio was the Editor-in-Chief of the IEEE TRANSACTIONSON CIRCUITS AND SYSTEMS—II for 1997–1999. He is co-recipient of the 1995Guillemin–Cauer award and the 1997 Darlington Award.