PUTTING CUSTOMERS FIRST - UMC

IP FocusArtisan & UMC Collaborate on PCIExpress Compliant 0.13um PHY CoreThe collaborative effortsbetween Artisan Componentsand UMC for IPand design resources haveshifted towards the developmentof a PCI Express TM PHY IP corefor 0.13-micron chip designs.The new core will be based onthe PCI Express Architecturethat has been proposed by thePCI-SIG® (PCI Special InterestGroup), which owns andmanages PCI specifications asopen industry standards.Based on Artisan’s siliconprovenXAUI compatible SerDesCore, the PHYs modulararchitecture enables a broadrange of computing andcommunications targetapplications emphasizingperformance, cost andscalability. The open architectureof the PCI Express to which thisoffering will comply will helpdesigners more easily integratethe core into their 0.13umproduct designs, and will offerthe benefits of high performanceand design flexibility.The PCI-Express TM 2.5GbpsPHY targets UMC’s 0.13-micronprocess technology. Themodular 8-lane PCI Express TM2.5Gbps PHY is designed to bea general-purpose I/Ointerconnect for “in-the-box”applications. Its architectureprovides a connectivity solutionfor adapter cards, attach pointsfor graphics I/Os as well as anI/O attach point for otherinterconnects like 1394b, USB2.0, Infiniband and Ethernet. ThePCI Express PHY creates acomplete serial link includingmux/demux, 8b/10b encode/decode and clock recoverycircuitry which is compliant withthe PCI Express Specification.The core is slated for availabilityto customers in the fourth quarterof 2003.About PCI ExpressPCI Express architectureis a state-of-the-art serialinterconnect technology thatkeeps pace with recent advancesin processor and memorysubsystems. From its initialrelease at 0.8V, 2.5GHz, the PCIExpress technology roadmap willcontinue to evolve, whilemaintaining backward compatibility,well into thenext decade with enhancementsto itsprotocol, signaling,electromechanical andother specifications.The PCI Expressarchitecture retains thePCI usage model andsoftware interfaces forinvestment protection andsmooth development migration.The technology is aimedat multiple market segments inthe computing and communicationindustries, andsupports chip-to-chip, board-toboardand adapter solutions atan equivalent or lower coststructure than existing PCIdesigns. PCI Express currentlyruns at 2.5Gbps, or 250MBpsper lane in each direction,providing a total bandwidth of16GBps in a 32-laneconfiguration. Future frequencyincreases will scale up totalbandwidth to the limits of copperand significantly beyond that viaother media without impactingany layers above the PhysicalLayer in the protocol stack. PCIExpress provides I/O attachpoints for high-performancegraphics, 1394b, USB 2.0,InfiniBand Architecture,Gigabit networking and so on.PROFOUNDRY SPRING 20035