DAC0830/DAC0831/DAC0832 8-Bit MuP Compatible, Double ...

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Linearity Errora) End point test afterzero and fs adjTLH5608–3b) Best straight line c) Shifting fs adj to passbest straight line testDefinition of TermsResolution Resolution is directly related to the number ofswitches or bits within the DAC For example the DAC0830has 28 or 256 steps and therefore has 8-bit resolutionLinearity Error Linearity Error is the maximum deviationfrom a straight line passing through the endpoints of theDAC transfer characteristic It is measured after adjustingfor zero and full-scale Linearity error is a parameter intrinsicto the device and cannot be externally adjustedNational’s linearity ‘‘end point test’’ (a) and the ‘‘beststraight line’’ test (bc) used by other suppliers are illustratedabove The ‘‘end point test’’ greatly simplifies the adjustmentprocedure by eliminating the need for multiple iterationsof checking the linearity and then adjusting full scaleuntil the linearity is met The ‘‘end point test’’ guaranteesthat linearity is met after a single full scale adjust (One adjustmentvs multiple iterations of the adjustment) The ‘‘endpoint test’’ uses a standard zero and FS adjustment procedureand is a much more stringent test for DAC linearityPower Supply Sensitivity Power supply sensitivity is ameasure of the effect of power supply changes on the DACfull-scale outputSettling Time Settling time is the time required from a codetransition until the DAC output reaches within gLSB ofthe final output value Full-scale settling time requires a zeroto full-scale or full-scale to zero output changeFull-Scale Error Full scale error is a measure of the outputerror between an ideal DAC and the actual device outputIdeally for the DAC0830 series full-scale is V REF b1LSBFor V REF e10V and unipolar operation V FULL-SCALE e100000Vb39mVe9961V Full-scale error is adjustable tozeroDifferential Nonlinearity The difference between any twoconsecutive codes in the transfer curve from the theoretical1 LSB is differential nonlinearityMonotonic If the output of a DAC increases for increasingdigital input code then the DAC is monotonic An 8-bit DACwhich is monotonic to 8 bits simply means that increasingdigital input codes will produce an increasing analog outputFIGURE 1 DAC0830 Functional DiagramTLH5608–46
Typical Performance CharacteristicsDigital Input Thresholdvs TemperatureDigital Input Thresholdvs V CCGain and Linearity ErrorVariation vs TemperatureGain and Linearity ErrorVariation vs Supply Voltage Write Pulse Width Data Hold TimeDAC0830 Series Application HintsThese DAC’s are the industry’s first microprocessor compatibledouble-buffered 8-bit multiplying D to A convertersDouble-buffering allows the utmost application flexibilityfrom a digital control point of view This 20-pin device is alsopin for pin compatible (with one exception) with theDAC1230 a 12-bit MICRO-DAC In the event that a system’sanalog output resolution and accuracy must be upgradedsubstituting the DAC1230 can be easily accomplishedBy tying address bit A 0 to the ILE pin a two-byte mPwrite instruction (double precision) which automatically incrementsthe address for the second byte write (startingwith A 0 e‘‘1’’) can be used This allows either an 8-bit or the12-bit part to be used with no hardware or software changesFor the simplest 8-bit application this pin should be tiedto V CC (also see other uses in section 11)Analog signal control versatility is provided by a precision R-2R ladder network which allows full 4-quadrant multiplicationof a wide range bipolar reference voltage by an applieddigital word10 DIGITAL CONSIDERATIONSA most unique characteristic of these DAC’s is that the 8-bitdigital input byte is double-buffered This means that thedata must transfer through two independently controlled 8-bit latching registers before being applied to the R-2R laddernetwork to change the analog output The addition of asecond register allows two useful control features First anyDAC in a system can simultaneously hold the current DACdata in one register (DAC register) and the next data word inthe second register (input register) to allow fast updating ofthe DAC output on demand Second and probably moreimportant double-buffering allows any number of DAC’s in aTLH5608–5system to be updated to their new analog output levelssimultaneously via a common strobe signalThe timing requirements and logic level convention of theregister control signals have been designed to minimize oreliminate external interfacing logic when applied to mostpopular microprocessors and development systems It iseasy to think of these converters as 8-bit ‘‘write-only’’ memorylocations that provide an analog output quantity All inputsto these DAC’s meet TTL voltage level specs and canalso be driven directly with high voltage CMOS logic in nonmicroprocessorbased systems To prevent damage to thechip from static discharge all unused digital inputs shouldbe tied to V CC or ground If any of the digital inputs areinadvertantly left floating the DAC interprets the pin as alogic ‘‘1’’11 Double-Buffered OperationUpdating the analog output of these DAC’s in a double-bufferedmanner is basically a two step or double write operationIn a microprocessor system two unique system addressesmust be decoded one for the input latch controlledby the CS pin and a second for the DAC latch which iscontrolled by the XFER line If more than one DAC is beingdriven Figure 2 the CS line of each DAC would typically bedecoded individually but all of the converters could share acommon XFER address to allow simultaneous updating ofany number of DAC’s The timing for this operation isshown Figure 3It is important to note that the analog outputs that willchange after a simultaneous transfer are those from theDAC’s whose input register had been modified prior to theXFER command7
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