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CJTAG for concurrent test/programming on a single PCBDDRDDRDDRDDRDSPDDRDDRDDRDDRDDRDDRDDRDDRDDRDDRDDRDDRDSPDSPDSPCJTAGControllerTDO/EXPTCKTMSTDITRST/MASKCJTAGICDDRDDRDDRDDRDDRDDRDDRDDRDDRDDRDDRDDRDSPDDRDDRDDRDDRDSPDSPDSPBoard Test Work Shop 2006
LSP0 LSP1 LSPNTDIATL0ATL1ATLNBrake[n:0]Local Scan Path MatrixTDOMASKTRST*ORATL_ADDR[n:0]EnableMDIEnableTRST* TMS TCK Path SelectCMPResults[n:1]FAIL[n:0]EDIADI[n:0]SHIFTDR*SHIFTIR*ATLATLTLRATL0TLRTLRSAD[7:0]ATL_ADDR[n:0]CJTAGCFG/CMPCFSLOT_ADDRPATH SELECTDevice IDBypassBOUNDARYTDOEN1EXPTDOTDITMSTCKTRST*TAPControllerClockIRUpdateIRShiftIR*Reset*SelectTDOENShiftDR*UpdateDRClockDRInstruction RegisterCJTAG_ON*TDOEN1SHIFTDR*SHIFTIR*EnableBoard Test Work Shop 2006
Page 2: Problem: 1149.1 Data Volume require
Page 7 and 8: Total Test Time = ~10 sec = 10secs
Page 9 and 10: 10In Multi-drop 1149.1, TDO is not
Page 11 and 12: Total Test Time = ~10 sec TDO becom
Page 13 and 14: Multi-drop bus major disadvantage i
Page 15 and 16: LSP0 LSP1 LSPNBrakeTDI Local Scan P
Page 17 and 18: 1 TCK delay fromPCB 1 & 21 TCK dela
Page 19: ResultsSystemDescriptionPCBConfigur
Page 23 and 24: Broad architecture - not wires can

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