6-Joyce-Board Test Workshop 2005.pdf

Board Test Workshop 2005Board Flex InitiativeFrank W JoyceStaff Mechanical EngineerCore Technology Program ManagerIntel® Test Development Engineering1

Agenda1. Introduction to Strain Measurement2. Overview of Intel® Board Flex Initiative (BFI)3. Test Equipment Requirements4. Demonstration5. Test Report Review6. Jedec 97047. Questions and Answers2

Intro to Strain testing• As BGA package size and ball pitch have decreased, second-level interconnect failure due to manufacturing over-flexurehas become an increasing concern, especially whencombined with the metallurgical changes for lead freemanufacturing.• Data suggests typical manufacturing processes may exceedstrain limits in one or more of these areas: Board Assembly,ICT, Functional Test and System Assembly• In Circuit Testing (ICT) has shown to induce the higheststrain.• Strain gage measurement is a common and effective way ofmonitoring board flexure, and Intel® is now establishingstrain limits for our BGA products.• Intel’s® BFI (Board Flex Initiative) is a set of tools that hasbeen carefully designed to correlate laboratory experimentaldata to the real world factory.3

Definition of Board Flexure• When a board is assembled it is stressed—andtherefore strained—in many directions. This“board flexure” puts stress on the solder jointsand causes the package to flex, too. The cornersolder balls are usually under the most stress.BGA PackageRegions ofroughly equalstress4Highest Stressis in the corner• We do not have a way to directly measure thestress or strain on the solder balls, so wemeasure the strain on the PCB near the cornerof the package.

How do we measure strain?• We measure strain using rectangular rosette straingages that measure 3 directions at once. (e1,e2,e3)• They work by measuring the resistance changethat occurs when a metal is strained.e3e2e15

What is Strain?• Strain is a measure of deformation, relative to the initial size.L1L2L2 –L1 = ∆LStrain is calculated using the formula ε = ∆L L / L1* which has no• Strain is calculated using the formulaunits since the lengths cancel out.• When ε = 0.000001, it is called 1 microstrain (µε).6

Strain Metrics• Since Strain is a dimensionless number, a precise metricmust be used to define the test values.• The value is based on careful lab testing and analytical FEAmethods.• Intel® uses a metric called diagonal strain. This metriccorrelates better to solder joint damage, regardless of bendmode, than a many other metrics, including principal strain.The worst case bend mode for rectangular FCBGAcomponents is Spherical bending.• The diagonal strain equation is:Max Diagonal Strain = MAX( |e2| , |e1+e3-e2|)**Defined as the Maximum of the absolute value of either e3, or e1+e3e1+e3-e2e27

Load on Corner JointA spherical bending condition isthe worst case1.000.800.600.400.20• Several bend modeswere tested.• Large variation wasseen in the strain atfailure• Spherical bend gavethe highest strain vs.joint stress0.000 0.2 0.4 0.6 0.8 1Board-Level Strain8

And is less bend mode sensitive• This metric isolates thestrain vectors mostresponsible for cornerjoint stress• This results in reducedstrain level variation atjoint failure, regardlessof bend mode,compared to principalstrainLoad on Corner Joint1.000.800.600.400.20εdiagonal= max( ) ( )ε2,εAlternatemetric1ε 3ε2ε 1ε 2+ ε3Principalstrain90.000 0.2 0.4 0.6 0.8 1Board-Level Strain

Strain Limit Determination• Intel® has begun providing strain limits for its BGA componentsto help manufacturers identify processes which cause high strain.• The limits are based upon a laboratory test in which pressure isapplied to the back of the component and around the componentin the opposite direction. We test for the strain at which cracksbegin, not just when the electrical connection is broken.10

Strain Limit Determination• Strain gages are attached to the test coupon at preciselocations, the coupon is bent to certain strains, and the jointsare tested for cracks.• The result is a strain value for a particular location which isrelative to the threshold of damage.Board strainOnset of crackingcomponent strain11

Strain Limit Definition• The test is designed to define the degree ofboard flex at which point board crack initiationbegins not when the an electrical open occurs.Example of over-flexed condition. Note the board crack.12

LF Solder vs Tin-Lead Eutectic SolderComparison in Transient BendTensile force on pad1SnAgCu (LF)23LF limit5IMCs InSn matrix4PbSn limitPCB micro-strains1LFPbSnSnPb Eutectic23Pad loadbearingcapabilityTwo PhaseStructure131. The solder ball joins the substrate and thePCB by material that behaves as a spring.Lead free solder has higher stiffness thanPbSn solder, analogous to having a robustthick-wire spring coil for lead-free comparedto a thin-wire spring for PbSn solder.2. The bottom of the solder ball is attached tothe PCB. The strength of the attach point isdetermined by pad size, PCB material andconstruction, etc. The interface strength (i.e.load bearing capability for pad crater mode)between the copper pad and PCB has notchanged between PbSn and LF.3. Board bending to a given micro-strain on thePCB is tantamount to pulling apart at anoblique angle the two opposite surfaces ofthe solder ball to a given amount.4. The higher stiffness lead-free ball generateshigher forces on the pad for the same applieddeflection. The softer PbSn balls deformsmore to accommodate the applied bending,resulting in lower forces acting on the pad fora given deflection level.5. Since pad adhesion strength has notchanged, lead-free ball reaches the criticallevel of force required to pull the pad out atlower strain. This is a consequence of the ballmaterial property, not the pad property.

Precise gage location is critical• Close to the joint thestrain field is highlynonlinear• Far from the joint thestrain field is notrepresentative• For typicalmotherboardapplications, 5mmfrom the package edgeworks well14StrainLinear RegionSteep,Nonlinear region3.6mmNot RepresentativeDistance from corner3.6mm5.0mme1e2e3

Intel® Board Flex InitiativeOverview• The Intel® Board Flex Initiative (BFI) consists of six documentsdescribing the theory and operation of board flex testing toreduce strain in the manufacturing environment.– Section 1 Introduction– Section 2 Gage Attach– Section 3 Calibration fixture– Section 4 Line testing– Section 5 Data Reduction• These documents are available from TDE or your local Intel®test representative.15

Desktop Components Strain LimitGuidance for Lead Free PackageProductPackagePitch(mm)PackageSize (mm)Boardthickness(in / mm)Pb-FreeStrainLimit (µε(µε)Intel® Broadwater GMCHFCBGA70.8+1.037.5 x 37.5.040” / 1.0.062” / 1.6600600Intel® ICH8 ChipsetPBGA1.07MM31X31.040” / 1.0.062” / 1.6*500*500Intel® Gb-LAB“Ninevah”FCMMAP1.010 x 10.040” / 1.0.062” / 1.6*500*450Intel® LGA775 Socket1.2745 x 45.040” / 1.0.062” / 1.6650600Important Note:Above strain limit is only valid when using measurement metrologydocumented in Intel Board Flexure MAS rev 3.01 or later.*Preliminary estimate16

Mobile Components Strain LimitGuidance for Lead Free PackageProductPackagePitch(mm)PackageSize (mm)Boardthickness(in / mm)Pb-FreeFreeStrainLimit (µε(µε)Intel® Mobile 945 MCHChipset0.8+37.5 x 37.5.040” / 1.0.062” / 1.6650600**Intel® ICH7M Chipset(Plastic Ball Grid Array)1.0731X31.040” / 1.0.062” / 1.6500500Intel® Pentium® MProcessor in Micro-FCBGA Package (Yonah(Based)1.2735 x 35.040” / 1.0.062” / 1.6*650*650Important Note: Above strain limit is only valid when using measurementmetrology documented in Intel Board Flexure MAS rev 3.0 or later*Assume Solder Mask Defined pads are used at corner.**Not a FCBGA package, PBGA package.17

Server Components Strain LimitGuidance for Lead Free PackageProductPackagePitch(mm)PackageSize (mm)Boardthickness(in / mm)Pb-FreeStrainLimit (µε(µε)Enterprise SouthbridgeESB-21.040.0 x 40.0.092” / 1.0.062” / 1.6550600GMCH NorthbridgeBlackford/Greencreek1.0942.5X42.51.092” / 1.0.062” / 1.6550600Socket LGA771.092” / 1.0*6001.2745 x 45.062” / 1.6*65018

Test Equipment Requirements• Data recorder parameters:– Minimum sample rate:– 500HZ for ICT–200HZ for Functional Test–½ rate if digital filter used.– Channel Sample Setup:–Minimum 3 channels–All Channels simultaneously• The Data recorder must output the following 4 parameters foreach gage:– Time (t), in seconds– Strain 1 (e1) in microstrain– Strain 2 (e2) in microstrain– Strain 3 (e3) in microstrain– The file can be a .TXT, or .XLS format.– 3 sample measurements run for each component19

Gage Locations• BGA rosette placement 4 gages– MCH, ICH, LAN or defined componentOffset from the packageedge 0.14”e1e2e32 133211 2 3 1 2 3• The center of the rosetteshould be placed at theintersection of two linesoffset from the package edge0.14” +/- 0.01”• Grid strains e1 and e3should be oriented parallel tothe edges of the package.• e2 should be orienteddiagonally away frompackage, with respect to theedges of the package, asshown.20

Gage Locations• LGA 775 socket- 2 gages only– rosette placement1 2 31 23• Attach rosettes at the twocorners nearest the lever end.Offset from the packageedge 0.27”e1e2e3• Place the rosette centers atthe intersection of two linesoffset from the componentpackage edges .27” +/- .01”• Orient rosettes as shown onthe previous slide.21

Data Report• Data report is to be in one of the following Intel® Formats:– MAS 3.01 Section 5• Data required in report:– Component identification– Board Identification– Component location– Gage make and type– MAX value E1,E2,E3– MAX DIAGONAL STRAIN for each corner– Digital Photo of each gage location– Graph of strain measurement from data acquisition system. Shouldcontain e1, e2, e3, and if possible e4.– Components measured-MCH, ICH, LGA77522

Demonstration• Flex test run #1• Diagonal Strain data reduction• Strain Graph creation• Report23

Sample Report24

Sample Report25

Data Reduction Demo26

Gage Locations27

Strain Graph• Single corner 3 gage rectangular rosette data reduction graph28

JEDEC 9704• Jedec Spec29

Future• Alternate gage locations– Mobile and Handheld• Tier 2 training videos• Inclusion of 9-point 9bend into JEDEC30

Backup31