Hitachi H8/3292

15.2.2 Exit from Sleep ModeThe chip exits sleep mode when it receives an internal or external interrupt request, or a low input at the5(6 or 67%< pin.(1) Exit by Interrupt: An interrupt releases sleep mode and starts the CPU’s interrupt-handlingsequence.If an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable bit inthe module’s control register, the interrupt cannot be requested, so it cannot wake the chip up. Similarly,the CPU cannot be awoken by an interrupt other than NMI if the I (interrupt mask) bit is set when theSLEEP instruction is executed.(2) Exit by 5(6 pin: When the 5(6 pin goes low, the chip exits from sleep mode to the reset state.(3) Exit by 67%< pin: When the 67%< pin goes low, the chip exits from sleep mode to hardwarestandby mode.15.3 Software Standby Mode15.3.1 Transition to Software Standby ModeTo enter software standby mode, set the standby bit (SSBY) in the system control register (SYSCR) to 1,then execute the SLEEP instruction.In software standby mode, the system clock stops and chip functions halt, including both CPU functionsand the functions of the on-chip supporting modules. Power consumption is reduced to an extremely lowlevel. The on-chip supporting modules and their registers are reset to their initial states, but as long as aminimum necessary voltage supply is maintained, the contents of the CPU registers and on-chip RAMremain unchanged.15.3.2 Exit from Software Standby ModeThe chip can be brought out of software standby mode by by 5(6 input, 67%< input, or externalinterrupt input at the 10, pin, IRQ0 to IRQ2 pins.(1) Exit by Interrupt: When an NMI, IRQ0, IRQ1,or IRQ2 interrupt request signal is input, the clockoscillator begins operating. After the waiting time set in bits STS2 to STS0 of SYSCR, a stable clock issupplied to the entire chip, software standby mode is released, and interrupt exception-handling begins.(2) Exit by 5(6 Pin: When the 5(6 input goes low, the clock oscillator begins operating. When 5(6 isbrought to the high level (after allowing time for the clock oscillator to settle), the CPU starts resetexception handling. Be sure to hold 5(6 low long enough for clock oscillation to stabilize.(3) Exit by 67%< Pin: When the 67%< input goes low, the chip exits from software standby mode tohardware standby mode.223