Hitachi H8/3292

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Table 2-2 Effective Address Calculation (cont)No.Addressing Mode andInstruction FormatEffective Address Calculation Effective address5 Absolute address158 7 0@aa:8H'FF158 7 0opabs@aa:1615op0150abs6Immediate#xx:815op8 7 0IMM#xx:1615op0Operand is 1- or 2-byte immediate dataIMM7PC-relative@(d:8, PC)15PC contents015015op8 7 0dispSign extensiondisp30
Table 2-2 Effective Address Calculation (cont)Addressing Mode andNo. Instruction FormatEffective Address Calculation Effective Address8 Memory indirect, @@aa:815op8 7 0abs158 7 0H'00Memory contents (16 bits)150Legendreg: General registerop: Operation codedisp: DisplacementIMM: Immediate dataabs: Absolute address31
Page 1 and 2: Hitachi Single-Chip MicrocomputerH8
Page 3 and 4: ContentsPreface...................
Page 5 and 6: Section 7 I/O Ports ...............
Page 10 and 11: viii
Page 13 and 14: Section 1 Overview1.1 OverviewThe H
Page 15 and 16: Table 1-1 Features (cont)ItemSpecif
Page 17 and 18: 1.2 Block DiagramFigure 1-1 shows a
Page 19 and 20: 1.3.2 Pin Functions(1) Pin Assignme
Page 21 and 22: Table 1-2 Pin Assignments in Each O
Page 23 and 24: Table 1-3 Pin Functions (cont)TypeS
Page 25 and 26: Table 1-3 Pin Functions (cont)TypeS
Page 27: 17605958575655545352515049484746454
Page 30 and 31: 2.1.2 Address SpaceThe H8/300 CPU s
Page 32 and 33: 2.2.2 Control RegistersThe CPU cont
Page 34 and 35: 2.3.1 Data Formats in General Regis
Page 36 and 37: 2.4 Addressing Modes2.4.1 Addressin
Page 38 and 39: 2.4.2 Calculation of Effective Addr
Page 42 and 43: 2.5 Instruction SetThe H8/300 CPU h
Page 44 and 45: 2.5.1 Data Transfer InstructionsTab
Page 46 and 47: 2.5.3 Logic OperationsTable 2-6 des
Page 48 and 49: 2.5.5 Bit ManipulationsTable 2-8 de
Page 50 and 51: Before Execution of BCLR Instructio
Page 52 and 53: 2.5.6 Branching InstructionsTable 2
Page 54 and 55: 2.5.7 System Control InstructionsTa
Page 56 and 57: Notes on EEPMOV Instruction1. The E
Page 58 and 59: 2.6.2 Program Execution StateIn thi
Page 60 and 61: Bus cycleT 1 stateT 2 stateøAddres
Page 62 and 63: Write cycleT 1 state T 2 state T 3
Page 64 and 65: 3.2 System Control Register (SYSCR)
Page 66 and 67: 3.4 Address Space Map in Each Opera
Page 68 and 69: 58Figure 3-3 H8/3294 Address Space
Page 71 and 72: Section 4 Exception Handling4.1 Ove
Page 73 and 74: Vector fetchInternalprocessingInstr
Page 75 and 76: Table 4-2 InterruptsInterrupt sourc
Page 77 and 78: IRQ Enable Register (IER)BitInitial
Page 79 and 80: NMI interruptInterrupt controllerCP
Page 81 and 82: SP - 4SP - 3SP - 2SP(R7)SP + 1SP +
Page 83: CPU writecycle to TIEROCIA interrup
Page 86 and 87: 5.1.4 Register ConfigurationTable 5
Page 88 and 89: Inserted bywait countInserted byWAI
Page 90 and 91:
Bits 7 and 6—ReservedBit 5—Cloc
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(2) Input of External Clock Signal1
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6.3 Duty Adjustment CircuitWhen the
Page 96 and 97:
Table 7-1 Port FunctionsExpanded Mo
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7.2.2 Register Configuration and De
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Mode 2: In mode 2 (expanded mode wi
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Port 2 pinsPin configurationin mode
Page 104 and 105:
7.3.3 Pin Functions in Each ModePor
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Port 4Port 4 pinsP4 7 /WAITP4 6 /ø
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7.4.3 Pin Functions in Each ModePor
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7.5 Port 47.5.1 OverviewPort 4 is a
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7.5.3 Pin FunctionsPort 4 has one s
Page 114 and 115:
Page 116 and 117:
Page 118 and 119:
7.7.3 Pin FunctionsPort 6 has the s
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Page 122 and 123:
8.1.2 Block DiagramFigure 8-1 shows
Page 124 and 125:
Table 8-2 Register Configuration (c
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Table 8-3 Buffered Input Capture Ed
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8.2.5 Timer Control/Status Register
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Bit 1—Timer Overflow Flag (OVF):
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8.2.7 Timer Output Compare Control
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(1) Upper byte writeCPU writesdata
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8.4.2 Output Compare TimingWhen a c
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(2) Buffered Input Capture Timing:
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8.4.7 Setting of FRC Overflow Flag
Page 142 and 143:
(2) Contention between FRC Write an
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Table 8-5 Effect of Changing Intern
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Externalclock sourceTMCIInternalclo
Page 148 and 149:
9.2.2 Time Constant Registers A and
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Bits 2, 1, and 0—Clock Select (CK
Page 152 and 153:
Bits 3 to 0—Output Select 3 to 0
Page 154 and 155:
9.3.2 Compare Match Timing(1) Setti
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9.4 InterruptsEach channel in the 8
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9.6.2 Contention between TCNT Write
Page 160 and 161:
9.6.5 Incrementation Caused by Chan
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152
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10.1.3 Register ConfigurationTable
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Bits 2—0: Clock Select (CKS2-CKS0
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10.3.2 Interval Timer ModeInterval
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160
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11.1.2 Block DiagramFigure 11-1 sho
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11.2.3 Transmit Shift Register (TSR
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Bit 2—Multiprocessor Mode (MP): T
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Bit 3MPIE Description0 The multipro
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Bit 4—Framing Error (FER): This b
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Tables 11-3 and 11-4 show examples
Page 184 and 185:
Table 11-3 Examples of BRR Settings
Page 186 and 187:
11.2.9 Serial/Timer Control Registe
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Table 11-6 SCI Clock Source Selecti
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(2) Clock: In asynchronous mode it
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• Transmitting Serial Data: Follo
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• Receiving Serial Data: Follow t
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(4) Multiprocessor CommunicationThe
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1StartbitData (ID1)MPBStopbitStartb
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• Transmitting Serial Data: Follo
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• Receiving Serial Data: Follow t
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• Transmitting and Receiving Seri
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(3) Line Break Detection: When the
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12.1.2 Block DiagramFigure 12-1 sho
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12.2 Register Descriptions12.2.1 A/
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Bits 2 to 0—Channel Select 2 to 0
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1. Single mode is selected (SCAN =
Page 216 and 217:
In scan mode, the values given in t
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208
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13.1.2 RAM Enable Bit (RAME) in Sys
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14.2 PROM Mode (H8/3297, H8/3294)14
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Address in MCU modeH'0000Address in
Page 226 and 227:
Table 14-6 AC Characteristics(when
Page 228 and 229:
14.3.3 Reliability of Programmed Da
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220
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BitInitial valueRead/Write7SSBY0R/W
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15.3.3 Clock Settling Time for Exit
Page 236 and 237:
15.4.3 Timing RelationshipsFigure 1
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Table 16-2 DC Characteristics (5-V
Page 240 and 241:
Page 242 and 243:
Page 244 and 245:
Table 16-5 Allowable Output Current
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Table 16-7 Bus TimingCondition A:VC
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Table 16-9 Timing Conditions of On-
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16.3 MCU Operational TimingThis sec
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(3) Clock Settling TimingøV CCSTBY
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(2) SCI Input Clock Timingt SCKWSCK
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Table A-1 Instruction SetAddressing
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Table A-1 Instruction Set (cont)Add
Page 260 and 261:
Page 262 and 263:
Page 264 and 265:
Table A-2 Operation Code MapLowHigh
Page 266 and 267:
Table A-4 Number of Cycles in Each
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Page 270 and 271:
Page 272 and 273:
(Continued from previous page)Bit N
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(Continued from preceding page)Bit
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B.2 Function DescriptionsRegister n
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TCSR—Timer Control/Status Registe
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TCR—Timer Control RegisterH'FF96
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ICRA (H and L)—Input Capture Regi
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TCNT—Timer Counter H’FFA9 (read
Page 286 and 287:
P4DR—Port 4 Data Register H'FFB7P
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STCR—Serial/Timer Control Registe
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MDCR—Mode Control Register H'FFC5
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TCSR—Timer Control/Status Registe
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TCR—Timer Control RegisterH'FFD0T
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SMR—Serial Mode RegisterH'FFD8SCI
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SCR—Serial Control Register H'FFD
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SSR—Serial Status Register H'FFDC
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ADCSR—A/D Control/Status Register
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294
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C.2 Port 2 Block DiagramResetHardwa
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C.4 Port 4 Block DiagramResetRQ DP4
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Hardware standbyMode 1 or 2ResetRQ
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WAIT input enableMode 1 or 2ResetRQ
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P5 2ResetRQ DP5 2 DDRCWP5DResetRQ D
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ResetRQ DP61 DDRCWP6DResetInternal
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ResetRQ DP64 DDRCWP6DResetInternal
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310
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Table D-1 Port States (cont)Pin Nam
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314
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Table F-1 H8/3297 Series Product Co
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Unit: mm17.2 ± 0.31448 33Unit: mm4
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Hitachi H8/3292

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