The PowerPC 604 RISC Microprocessor - eisber.net

Data addressInstruction address•Memory addressCopy-back addressCache control addressTable 2. The 604 physical characteristics.ItemAddress busData address♦ Instruction address AALine-fin address LI]Line-fill buffer (8 words)ASnoop addressFigure 8. Address and data queue organization.CharacteristicsInstructionData ARead dataWrite buffer(2 words)DataCopy-back buffer —(8 words)\ T T /AVData busIInclude setting instruction or dataaddress breakpoints. single stepping.running Ncycles. and reading and writingsystem memory locations a' well asany storage element within the processorThe COP functions are implementedas an extension to theIEEE-1149.1 specification. and are controlledentirely through that interfaceSystem designers can configure the604 processor operating frequency asone. one-and-a-half. two. or threetimes the system bus frequency. Theon-chip phase-locked loop generatesthe necessary processor clocks fromthe bus clock. The 604 also providesa nap mode, which clocks only externalinterrupt detection logic and thephase-locked loop. It enters napmode under software control andexits from the mode upon detectingan interrupt. The 60-4 can still servicesnoop requests if the system assertsthe RUN pin to run the clocks whilein the nap mode. We estimate napmode power consumption at less than 0.4 watts.Table 2 lists some of key physical characteristics of the604. Figure 9 shows the 604 die photo.TechnologyDie sizeTransistor countCache sizeVoltagePower dissipationSignal VOsPackage0.5-um CMOS, 4 metal layers196 mm ,, 12.4x15.8 mm3.6 million16-Kbyte I-cache and D-cache3.3V, 5V VO tolerantLess than 10W at 100 MHz171; C MOSITTL compatible304-pin CQFPwithout additional hardware. These functions can determinemany key performance parameters, such as instruction executionrate, branch prediction rate, cache hit rates, and averagecache miss latency.The 604 design follows the level-sensitive scan designmethodology to provide high test coverage. As required byLSSD rules, every storage element, except in arrays, connectsto a scan chain that starts with a chip input pin and ends on achip output pin. During test mode. storage elements in a scanchain behave as a shift register that can also capture inputs toexercise a sequential digital network in a combinational manner.The 604's common on-chip processor (COP) providesmany functions to control and observe the storage elements.Some of the functions useful for chip and system debuggingDESIGNED TO MEET LOW-COST needs of the personalcomputer market, the 604 performs well with inexpensive,as well as expensive. memory systems. The 604's large onchipcaches help to maintain performance of well-behavedapplications that exhibit localities. For those with erraticbehaviors and access patterns. speculative execution guidedby dynamic branch prediction helps to reduce on-chip cachemiss latency. The nonblocking execution pipelines and thememory queues that decouple the pipelines from memoryaccess further help to reduce the effects of cache misses. Thesplit and pipelined modes use the system bus to providegreater bandwidth while maintaining compatibility with the601 and 603 microprocessors. J!1References1. E. Silha, "The PowerPC Architecture." IBM RISC System/6000Technology: Volume II, IBM Corporation. Austin, Tex., 1993.2. C Moore, "The PowerPC 601 Microprocessor," IBM RISCSystem/6000 Technology. Volume II, IBM Corporation. 1993.3 B. Burgess et al., "The PowerPC 603 Microprocessor - A HighPerformance, Low Power. Superscalar RISC Microprocessor."16 IEEE Micro