Xtrinsic MMA8653FC 3-Axis, 10-bit Digital Accelerometer - Freescale

2. Note that the first sample is typically not very precise; only the second or third or fourth sample (depending on ODR/MODS settings) has full
precision.
2.4 I 2 C interface characteristics
MMA8653FC
Table 6. I 2 C slave timing values (1)
Parameter Symbol
1. All values referred to VIH (min) and VIL (max) levels.
2. This device does not stretch the LOW period (tLOW) of the SCL signal.
3. tVD;DAT = time for Data signal from SCL LOW to SDA output.
4. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
5. Cb = total capacitance of one bus line in pF.
Figure 5. I 2 C slave timing
I 2 C Fast Mode
Min Max
SCL Clock Frequency f SCL 0 400 kHz
Bus Free Time between STOP and START condition t BUF 1.3 μs
(Repeated) START Hold Time t HD;STA 0.6 μs
(Repeated) START Setup Time t SU;STA 0.6 μs
STOP Condition Setup Time t SU;STO 0.6 μs
SDA Data Hold Time t HD;DAT 0.05 0.9 (2)
SDA Valid Time (3)
SDA Valid Acknowledge Time (4)
Sensors
10 Freescale Semiconductor, Inc.
Unit
t VD;DAT 0.9 (2) μs
t VD;ACK 0.9 (2) μs
SDA Setup Time t SU;DAT 100 ns
SCL Clock Low Time t LOW 1.3 μs
SCL Clock High Time t HIGH 0.6 μs
SDA and SCL Rise Time t r 20 + 0.1 C b (5)
μs
300 ns
SDA and SCL Fall Time t f 20 + 0.1 C b (5) 300 ns
Pulse width of spikes on SDA and SCL that must be suppressed by
internal input filter
handbook, full pagewidth
SDA
SCL
t f
t LOW
t r
t SU;DAT
tHD;STA tSU;STA S
tHD;DAT tHIGH Sr
t f
t SP 0 50 ns
t HD;STA
t SP
t SU;STO
t r
t BUF
P S
MSC610