Xtrinsic MMA8653FC 3-Axis, 10-bit Digital Accelerometer - Freescale

6.8.5 0x2E: CTRL_REG5, Interrupt Configuration Register (Read/Write)
This register maps the desired interrupts to INT2 or INT1.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INT_CFG_ASL — — INT_CFG_LNDP — INT_CFG_FF_M 0 INT_CFG_DRD
MMA8653FC
Figure 42. 0x2E: CTRL_REG5, Interrupt Configuration Register
Table 41. CTRL_REG5 register
Field Description
INT_CFG_ASLP Auto-SLEEP/WAKE INT1/INT2 Configuration
INT_CFG_LNDPRT Orientation INT1/INT2 Configuration
INT_CFG_FF_MT Freefall/motion INT1/INT2 Configuration
INT_CFG_DRDY Data Ready INT1/INT2 Configuration
0 Interrupt is routed to INT2 pin (default)
1 Interrupt is routed to INT1 pin
The system’s interrupt controller shown in Figure 10 "System interrupt generation" uses the corresponding bit field in the
CTRL_REG5 register to determine the routing table for the INT1 and INT2 interrupt pins. If the bit value is logic ‘0’ the functional
block’s interrupt is routed to INT2, and if the bit value is logic ‘1’ then the interrupt is routed to INT1. One or more functions can
assert an interrupt pin; therefore a host application responding to an interrupt should read the INT_SOURCE (0x0C) register to
determine the appropriate sources of the interrupt.
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46 Freescale Semiconductor, Inc.